Cap Layer Composition for Low-k Damascene Polishing Damage

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Solution Overview

Problem

Low-k dielectric materials in semiconductor devices are prone to damage during processing, leading to leakage paths that reduce electrical performance due to RC delay issues.

Innovation Solution

A cap layer with a carbon atom content ranging from 20% to 35% or 0% to 5% is formed over the low-k dielectric layer, providing improved hardness and damage resistance during polishing processes, thereby reducing leakage current and enhancing the RC delay performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If low-k dielectric materials are used to reduce RC delay, then electrical performance is improved, but damage resistance during polishing processes deteriorates

Engineering Contradiction:
Improveelectrical performanceVSAvoiddamage resistance
Core Design Contradiction:
ReliabilityVSStrength

Solution Approach 1:

The patent applies composite materials by forming a cap layer with different material composition (higher carbon atom content) on top of the low-k dielectric layer. This composite structure combines the low-k material's excellent electrical performance with the cap layer's superior hardness and damage resistance, resolving the contradiction between electrical performance and mechanical strength.

Inventive Principle:
Principle #40Composite materials

Solution Approach 2:

The patent applies local quality by creating a cap layer with specific local properties (higher carbon content, greater hardness) only at the surface region where polishing damage occurs. The underlying low-k dielectric layer maintains its original properties for electrical performance, thus achieving different quality characteristics in different regions to satisfy both requirements.

Inventive Principle:
Principle #3Local quality

2Reliability

If low-k dielectric materials are used to reduce RC delay, then electrical performance is improved, but surface dishing during polishing worsens

Engineering Contradiction:
Improveelectrical performanceVSAvoidsurface dishing
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The cap layer acts as an intermediary between the polishing pad and the low-k dielectric layer. It absorbs the mechanical stress and friction during polishing, preventing direct contact and damage to the low-k material surface, thereby eliminating surface dishing while preserving the low-k layer's electrical properties.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The cap layer provides localized protective quality at the surface region where polishing occurs, while the bulk low-k dielectric layer maintains its original structure and electrical characteristics. This spatial differentiation of properties resolves the contradiction between electrical performance and surface quality.

Inventive Principle:
Principle #3Local quality

3Reliability

If low-k dielectric materials are used to reduce RC delay, then electrical performance is improved, but leakage current increases

Engineering Contradiction:
Improveelectrical performanceVSAvoidleakage current
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent converts the potential harm of surface damage into a benefit by intentionally creating a cap layer with different composition that prevents leakage paths. The cap layer's higher carbon content creates a more stable, less porous surface structure that blocks leakage current, while the underlying low-k layer continues to provide low RC delay performance.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Data Source

PatentUS11929329B2Damascene process using cap layer
Publication Date: 2024.03.12 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11929329B2 patent drawing
  • US11929329B2 patent drawing
  • US11929329B2 patent drawing

AI summary

A semiconductor device including a substrate, a low-k dielectric layer, a cap layer, and a conductive layer is provided. The low-k dielectric layer is disposed over the substrate. The cap layer is disposed on the low-k dielectric layer, wherein a carbon atom content of the cap layer is greater than a carbon atom content of the low-k dielectric layer. The conductive layer is disposed in the cap layer and the low-k dielectric layer.