III-Nitride Transistor Cap Layer for RF Off-State Capacitance
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Solution Overview
Problem
Conventional silicon-based power devices are limited by high resistance and low critical electric field, restricting their operating frequencies and performance in high-current, high-voltage, and high-frequency applications, particularly in RF switching where off-state capacitance between source and drain terminals is a significant bottleneck.
Innovation Solution
A transistor structure is developed using a cap layer to extend the electrical distance between the gate and source/drain contacts, with a dielectric layer and vias allowing selective gate contact, and a field plate to reduce off-state capacitance, while the gate electrode contacts only a portion of the cap layer, allowing for reduced capacitance and modified gate leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a conventional transistor structure is used without a cap layer, then the device structure is simpler, but the off-state capacitance between source and drain terminals is higher
Solution Approach 1:
A cap layer is introduced as an intermediary element between the gate electrode and the source/drain contacts. This cap layer extends the electrical distance between the gate and the source/drain terminals, thereby reducing the off-state capacitance. The cap layer acts as a mediator that modifies the electrical field distribution without directly contacting the source or drain, achieving capacitance reduction while maintaining device functionality.
Solution Approach 2:
The cap layer extends in the lateral dimension beyond the gate electrode footprint, creating an extended region that increases the effective electrical distance between gate and source/drain terminals. By adding this dimensional extension, the patent reduces the capacitive coupling without increasing the vertical stack height, thus managing capacitance through spatial distribution in another dimension.
2Ease of operation
If the gate electrode contacts the entire cap layer, then the gate control is more comprehensive, but the off-state capacitance is higher
Solution Approach 1:
The gate electrode is designed to contact only a specific portion of the cap layer rather than the entire cap layer. This localized contact strategy allows the gate to control the channel effectively while minimizing the capacitive coupling area between the gate and source/drain terminals. The non-contact portions of the cap layer extend laterally to further increase electrical distance without compromising gate control.
Solution Approach 2:
Instead of the gate electrode contacting the full extent of the cap layer, only a partial contact is implemented. This partial action is sufficient to achieve the desired gate control over the active channel region while avoiding excessive capacitance that would result from full contact. The cap layer extends beyond the contact region to provide additional capacitance reduction benefit.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the performance of III-Nitride semiconductor devices by lowering off-state capacitance, improving frequency performance, and allowing for better control of gate capacitance and leakage, thereby overcoming the limitations of conventional silicon-based devices.
Implementation Method 1
electrons are formed at an interface between the channel layer and the barrier layer
Implementation Method 2
a dielectric layer may be disposed between the gate electrode and the cap layer
Implementation Method 3
a transistor structure that lowered the off-state capacitance between these terminals
Data Source
AI summary
This disclosure describes the structure of a transistor that provides improved performance by reducing the off-state capacitance between the source and the drain by using a cap layer to extend the electrical distance between the gate and the source and drain contacts. In certain embodiments, a dielectric layer may be disposed between the gate electrode and the cap layer and vias are created in the dielectric layer to allow the gate electrode to contact the cap layer at select locations. In some embodiments, the gate electrode is offset from the cap layer to allow a more narrow cap layer and to allow additional space between the gate electrode and the drain contact facilitating the inclusion of a field plate. The gate electrode may be configured to only contact a portion of the cap layer.