Cap Metal Layer for 3DIC TSV Diffusion and Cracking Prevention
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The semiconductor industry faces challenges in achieving efficient integration and reduced package height in three-dimensional integrated circuits (3DICs) due to high aspect ratio through-substrate vias, which lead to void and diffusion problems, and the need for advanced packaging with smaller form factors.
Innovation Solution
A front-to-back bonding method is employed, where semiconductor wafers are bonded with dielectric layers treated to form Si—OH bonds, followed by a thinning process and the formation of through-substrate vias (TSVs) with a cap metal layer to prevent metal diffusion and cracking, reducing the aspect ratio and package height.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If through-substrate vias (TSVs) are used to connect stacked dies in 3DICs, then integration density and bandwidth are improved, but high aspect ratio TSVs cause void and diffusion problems that reduce manufacturing reliability
Solution Approach 1:
The patent segments the TSV structure by introducing a cap metal layer that divides the via into two parts: the main via body and the capped portion. This segmentation allows the via to maintain electrical connectivity while preventing harmful metal diffusion in the upper portion, thus resolving the contradiction between achieving high integration density through TSVs and maintaining manufacturing reliability by preventing void and diffusion problems.
Solution Approach 2:
The cap metal layer acts as an intermediary element between the TSV fill metal and the surrounding dielectric material. It serves as a barrier that prevents metal diffusion into adjacent structures while maintaining the electrical pathway, thereby enabling high integration density without compromising manufacturing reliability.
2Length of stationary object
If package height is reduced to achieve smaller form factor, then portability and space utilization are improved, but manufacturing precision and defect control become more difficult
Solution Approach 1:
The cap metal layer is formed preliminarily during the TSV fabrication process, before final packaging and assembly. This preliminary action of capping the via prevents potential diffusion and void formation issues from occurring later, enabling reduced package height without sacrificing manufacturing precision or defect control.
3Reliability
If cap metal layer is added to TSV structure, then metal diffusion and cracking are prevented improving reliability, but device complexity and manufacturing steps increase
Solution Approach 1:
The cap metal layer formation is merged with the existing TSV fabrication process flow. The cap metal is deposited and patterned as an integrated step within the via formation sequence, combining the protective function with the interconnect fabrication rather than adding a completely separate process, thus improving reliability while minimizing the increase in device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances integration density, reduces void and diffusion issues, and achieves a smaller form factor for 3DICs by lowering the package height and preventing cracking, thereby improving the reliability and yield of the semiconductor device.
Implementation Method 1
semiconductor wafers are bonded with dielectric layers treated to form Si—OH bonds
Data Source
AI summary
Embodiments of mechanisms of forming a semiconductor device are provided. The semiconductor device includes a first semiconductor wafer comprising a first transistor formed in a front-side of the first semiconductor wafer. The semiconductor device also includes a second semiconductor wafer comprising a second transistor formed in a front-side of the second semiconductor wafer, and a backside of the second semiconductor wafer is bonded to the front-side of the first semiconductor wafer. The semiconductor device further includes an first interconnect structure formed between the first semiconductor wafer and the second semiconductor wafer, and the first interconnect structure comprises a first cap metal layer formed over a first conductive feature. The first interconnect structure is electrically connected to first transistor, and the first cap metal layer is configured to prevent diffusion and cracking of the first conductive feature.