Cap-Wafer Quantum Circuits for Qubit Noise Isolation

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Solution Overview

Problem

Current quantum computing systems face challenges in constructing and packaging microwave integrated quantum circuits that effectively isolate qubits from noise and maintain coherence, particularly due to the lossy nature of circuit wafers and external electromagnetic interference.

Innovation Solution

The use of cap wafers and electrically conducting vias to create a non-resonant cavity around quantum circuit devices, reducing participation ratios and enhancing coherence times by suppressing electromagnetic waves and substrate modes, while also employing bonding techniques like indium bumps for low-temperature operation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If quantum circuit devices are implemented on circuit wafers, then quantum computational tasks can be executed, but the circuit wafers are lossy and expose qubits to noise and external electromagnetic interference

Engineering Contradiction:
Improvecoherence timeVSAvoidnoise and electromagnetic interference
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

A cap wafer is bonded to the circuit wafer to form an enclosed cavity that shields quantum circuit devices from external electromagnetic interference and noise, while maintaining the functional integrity of the quantum circuits through controlled bonding interfaces

Inventive Principle:
Principle #30Flexible shells and thin films

Solution Approach 2:

The quantum circuit devices are enclosed within a cavity formed by bonding the cap wafer to the circuit wafer, creating a nested structure where the circuit wafer is contained within the larger assembly, providing progressive shielding and isolation

Inventive Principle:
Principle #7Nested doll (Nesting)

2Strength

If cap wafers are bonded to circuit wafers using conventional high-temperature techniques, then strong bonding is achieved, but quantum circuit devices are damaged due to high temperature exposure

Engineering Contradiction:
Improvebond strengthVSAvoiddevice integrity
Core Design Contradiction:
StrengthVSReliability

Solution Approach 1:

The bonding process is modified by using low-temperature indium bump bonding instead of conventional high-temperature techniques, changing the temperature parameter to be compatible with the quantum circuit devices while achieving sufficient bonding strength through the properties of indium

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

Indium bumps are melted and reflowed during the bonding process to achieve strong bonding between the cap wafer and circuit wafer, utilizing the phase transition of indium from solid to liquid and back to solid to create reliable electrical and mechanical connections

Inventive Principle:
Principle #36Phase transitions

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach improves the coherence times of quantum circuit devices by reducing loss and noise, enabling more robust and fault-tolerant quantum computing operations.

Implementation Method 1

reducing participation ratios and enhancing coherence times by suppressing electromagnetic waves and substrate modes

Methodology Applied
Scientific EffectElectromagnetic wave suppression: Resonance

Implementation Method 2

employing bonding techniques like indium bumps for low-temperature operation

Methodology Applied
Scientific EffectIndium bump bonding: Soldering

Data Source

PatentUS11770982B1Microwave integrated quantum circuits with cap wafers and their methods of manufacture
Publication Date: 2023.09.26 RIGETTI & CO INC
  • US11770982B1 patent drawing
  • US11770982B1 patent drawing
  • US11770982B1 patent drawing

AI summary

In a general aspect, an integrated quantum circuit includes a first substrate and a second substrate. The first substrate includes a first surface and a recess formed in the first substrate along the first surface. The recess has a recess surface and is configured to enclose a quantum circuit element. The first substrate includes a first electrically-conductive layer disposed on the first surface and covering at least a portion of the recess surface. The first electrically-conductive layer includes a first superconducting material. The second substrate includes a second surface and a quantum circuit element. The second substrate includes a second electrically-conductive layer on the second surface that includes a second superconducting material. The first substrate is adjacent the second substrate to enclose the quantum circuit device within the recess. The first electrically-conductive layer of the first substrate is electrically-coupled to the second electrically-coupled layer of the second substrate.