Cap Wafer Insulation Via Structure for Delamination Resistance
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Solution Overview
Problem
In semiconductor packages, the poor adhesion of conductive layers within vias due to thermal stress and electromigration leads to delamination at interfaces, compromising the reliability of the packages.
Innovation Solution
A semiconductor package design that includes a cap wafer mounted over a semiconductor wafer, with an insulation material overlaying the cap wafer and forming vias filled with a conductive material. This design reduces stress and improves adhesion by acting as a buffer layer and simplifying the photolithography process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metals of high electrical conductivity are used to form vias, then electrical conductivity is improved, but adhesion to other layers deteriorates due to thermal stress and electromigration
Solution Approach 1:
An insulation layer is introduced as an intermediary between the conductive via material and the surrounding layers. This insulation layer acts as a buffer that reduces thermal stress and prevents electromigration damage to adjacent layers, thereby maintaining both electrical conductivity and adhesion strength in the via structure.
Solution Approach 2:
The via structure is transformed from a single-material conductor into a composite structure consisting of a conductive core material surrounded by an insulating material layer. This composite approach allows the structure to simultaneously achieve high electrical conductivity through the conductive core and improved adhesion/stress resistance through the insulating layer.
2Reliability
If conductive layers are deposited within vias, then electrical connectivity is improved, but delamination occurs at interfaces due to thermal stress
Solution Approach 1:
The insulation layer serves as a protective intermediary between the conductive via material and the surrounding semiconductor layers. It absorbs and distributes thermal stress, preventing the propagation of stress to the interfaces where delamination would otherwise occur, thus maintaining interface stability while preserving electrical connectivity.
Solution Approach 2:
The insulation layer is applied beforehand to the via structure before subsequent processing steps. This pre-applied insulating layer acts as a cushion that anticipates and mitigates the thermal stress that will be introduced during later manufacturing or operation, preventing delamination before it can occur.
3Ease of manufacture
If conventional via formation processes are used, then manufacturing simplicity is maintained, but adhesion and stress resistance deteriorate
Solution Approach 1:
The insulation layer is applied to the via structure at an early stage in the manufacturing process, before subsequent conductive material deposition and processing steps. This preliminary action ensures that the protective insulating layer is in place to prevent adhesion failures and stress-related defects before they can occur during later manufacturing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution effectively reduces the risk of cracking due to stress and improves the coverage of conductive materials within the vias, enhancing the reliability and stability of semiconductor packages.
Implementation Method 1
via from one semiconductor component to another within an integrated electronic device
Implementation Method 2
various conductive layers or films are typically deposited on a semiconductor wafer by a process, such as electroplating
Data Source
AI summary
A semiconductor package includes a semiconductor wafer having a first connection pad and a second connection pad spaced apart by a semiconductor region of the semiconductor wafer. Portions of the semiconductor wafer are covered by a protective overcoat. The semiconductor package also includes a cap wafer mounted to the semiconductor wafer and overpassing the semiconductor region of the semiconductor wafer. The cap wafer extends between the first connection pad and the second connection pad of the semiconductor wafer. The semiconductor package further includes an insulation material overlaying the cap wafer. The insulation material comprising vias to the first connection pad and the second connection pad, the vias being filled with a conductive material.