Capacitance Adjusting Circuit for Semiconductor Bit Line Sensing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor devices, the open bit line method results in unequal load capacitance between bit lines and complementary bit lines, leading to sensing losses in bit line sense amplifiers due to dummy bit lines at the edge of memory cell arrays.
Innovation Solution
A semiconductor device with a capacitance adjusting circuit that uses control signals to adjust the load capacitance of complementary bit lines to match that of bit lines, employing capacitors and switches connected through transistors to minimize parasitic capacitance and optimize sensing performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the open bit line method is used to minimize chip area and allow memory cells to be disposed at each intersection, then the bit line sense amplifier can sense and amplify voltage difference between bit line and complementary bit line, but the load capacitance of the complementary bit line becomes unequal to that of the bit line due to dummy bit lines at the edge
Solution Approach 1:
The patent adjusts the load capacitance parameter of the complementary bit line by connecting different numbers of capacitors to match the bit line's load capacitance. This parameter matching resolves the sensing accuracy issue caused by unequal capacitance while preserving the open bit line architecture's area efficiency
Solution Approach 2:
The patent creates a copy of the bit line's load capacitance characteristics on the complementary bit line side by using identical capacitor structures. This copying approach ensures that both bit lines have matched load characteristics, eliminating the sensing loss caused by asymmetry
2Ease of manufacture
If dummy bit lines are present at the edge of the memory cell array, then the open bit line layout can be implemented with memory cells at each intersection, but the load capacitance balance between bit line and complementary bit line is disrupted
Solution Approach 1:
The patent implements a dynamic capacitance adjustment mechanism where capacitors are selectively connected or disconnected based on the specific bit line configuration. This dynamic approach allows the system to adapt to different layout scenarios and achieve precise capacitance matching despite the presence of dummy bit lines
Data Source
AI summary
A semiconductor device includes a bit line, a complementary bit line, a sense amplifier configured to sense and amplify a voltage difference between the bit line and the complementary bit line, and a capacitance adjusting circuit configured to adjust a load capacitance of the complementary bit line in response to a plurality of control signals.