Capacitance Processing Circuit for Normalized MEMS Sensor Readout
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Solution Overview
Problem
Conventional capacitive transducers in MEMS sensors face challenges in achieving high signal-to-noise levels without compromising linearity, particularly due to sensitivity to capacitor mismatches and reduced linearity in gap-modulated electrodes, which limits their performance in modern applications.
Innovation Solution
A processing circuit configuration that includes a current-to-voltage converter, successive gain stages, a reference voltage generator, and an analog-to-digital converter, which generates a normalized transfer function by processing parallel signals from capacitive transducer structures, effectively canceling common mode components and providing a linear and stable response.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional capacitive transducers use gap-modulated electrodes for differential detection, then signal-to-noise levels can be improved, but linearity is reduced and sensitivity to capacitor mismatches increases
Solution Approach 1:
The patent introduces an intermediary normalization process that divides the differential capacitance signal by the common-mode capacitance sum. This intermediary step (normalization division) mediates between the high signal-to-noise differential detection and the linearity requirement, producing a normalized output that is both sensitive and linear with respect to the measured quantity.
Solution Approach 2:
The patent transforms the output parameter from raw differential capacitance to normalized capacitance ratio. By changing the output parameter from (C1-C2) to (C1-C2)/(C1+C2), the system achieves both high signal-to-noise levels through differential detection and improved linearity through the normalized ratio, which has a linear relationship with the measured physical quantity.
2Measurement precision
If conventional capacitive transducers use differential detection with two capacitors, then accuracy is improved, but sensitivity to capacitor mismatches increases
Solution Approach 1:
The normalization division by common-mode capacitance (C1+C2) acts as an intermediary that compensates for capacitor mismatches. This intermediary process divides out the common-mode components including mismatch errors, allowing differential detection to maintain high accuracy while reducing sensitivity to capacitor mismatches.
Solution Approach 2:
The patent uses the common-mode capacitance sum as a feedback reference to normalize the differential signal. By continuously monitoring (C1+C2) and using it to scale the differential output (C1-C2), the system automatically compensates for mismatches and drifts, maintaining reliability while preserving the accuracy benefits of differential detection.
3Measurement precision
If conventional capacitive transducers amplify small signals, then detection capability is improved, but susceptibility to ambient interferences increases
Solution Approach 1:
The patent employs periodic modulation of the capacitor excitation signals at different frequencies. By modulating C1 and C2 with different periodic waveforms and detecting at specific frequencies, the system can amplify small signals while using frequency discrimination to reject ambient interferences that do not match the modulation frequencies.
Solution Approach 2:
The normalization process serves as an intermediary frequency-domain filter that separates the modulated differential signal from ambient interferences. By dividing the differential signal by the common-mode signal in the frequency domain, the system enhances detection capability while suppressing interference that appears as common-mode or non-modulated components.
Data Source
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AI summary
Processing circuit for processing input signals from a capacitive transducer structure. A current-to-voltage converter receives two input signals from the capacitive transducer structure, and outputs two output signals to gain stage circuits, and to a reference voltage generator. The gain stages generate from the output voltage signals a differential output signal. The reference voltage generates from the output signals a common mode output signal. The processing circuit generates a digital signal that corresponds to a quotient of the differential output signal and the common mode output signal.