Capacitance Element Design in 3D Stacked Nonvolatile Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The miniaturization of nonvolatile semiconductor memory devices requires increased design flexibility for capacitance elements, which existing technologies have not adequately addressed in the context of three-dimensional stacked memory devices.
Innovation Solution
A nonvolatile semiconductor memory device is designed with a capacitance element region that includes a stacked body of alternating electrode and insulating layers, where conductive layers and insulating films are strategically positioned to increase capacitance, allowing for the integration of capacitors within the device, thereby enhancing design flexibility and reducing the need for external capacitance elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If capacitance elements are integrated within the nonvolatile semiconductor memory device, then design flexibility increases, but device complexity increases
Solution Approach 1:
The patent merges the capacitance element structure with the existing memory device stacked body structure. Both the memory element and capacitance element share the same foundation layer and use identical alternating stacked bodies of electrode layers and insulating layers. This integration allows capacitance elements to be incorporated without adding separate external components, thereby increasing design flexibility while managing complexity through structural reuse.
2Area of stationary object
If capacitance elements are integrated within the device, then the area required for capacitance elements decreases, but manufacturing complexity increases
Solution Approach 1:
The manufacturing process merges the formation of memory elements and capacitance elements into a single integrated process flow. The same foundation layer, electrode layers, and insulating layers are formed for both element types simultaneously. This approach reduces the total area required while managing manufacturing complexity by using unified fabrication steps rather than separate processes.
Solution Approach 2:
The stacked body structure serves multiple functions: it forms both memory elements (with channel bodies and memory films) and capacitance elements (with conductive layers and insulating films). This multi-functionality allows the same structural framework to fulfill different electrical functions, reducing overall device area while streamlining manufacturing through universal process steps.
3Volume of moving object
If capacitance elements are integrated within the device, then overall device size decreases, but manufacturing precision requirements increase
Solution Approach 1:
The patent integrates capacitance elements within the same stacked body structure as memory elements, sharing common foundation layers, electrode layers, and insulating layers. This merging reduces overall device size by eliminating separate capacitance element structures. The manufacturing precision is managed through unified formation processes where the same layers serve dual purposes, reducing the need for additional precise alignment and fabrication steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases electrical capacitance, allowing for more flexible design options and reducing the area required for capacitance elements, which in turn decreases the overall device size and manufacturing complexity, while suppressing cost increases.
Implementation Method 1
a first capacitor and a second capacitor are provided in the capacitance element region. The first capacitor is made of one of the plurality of second insulating layers and a pair of the second electrode layers sandwiching the one of the plurality of second insulating layers, and the second capacitor is made of the second insulating film, and one of the plurality of second electrode layers and one of the plurality of conductive layers sandwiching the second insulating film
Data Source
AI summary
According to one embodiment, a nonvolatile semiconductor memory device includes a memory element region and a capacitance element region. The capacitance region including: a second stacked body, each of a plurality of second electrode layers and each of a plurality of second insulating layers being stacked alternately; a plurality of conductive layers; and a second insulating film provided between each of the plurality of conductive layers and each of the plurality of second electrode layers. In the capacitance element region, a first capacitor is made of one of the plurality of second insulating layers and a pair of the second electrode layers sandwiching the one of the plurality of second insulating layers, and a second capacitor is made of the second insulating film, and one of the plurality of second electrode layers and one of the plurality of conductive layers sandwiching the second insulating film.