Capacitance Extraction Using Library Lookup and Equation Solvers
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Solution Overview
Problem
Current Computer-Aided Design (CAD) tools for RC extraction face challenges in achieving high accuracy and speed, particularly when handling FinFET processes, and are not well-suited for complex integrated circuit (IC) layouts.
Innovation Solution
A method for capacitance extraction in IC layouts that decomposes nets into components, uses a library for pre-calculated capacitance lookup, and applies equation solvers on-the-fly for irregular cases, allowing for efficient and accurate calculation of net capacitance across various layers and geometries.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If current CAD tools are used for RC extraction, then the process can be completed, but accuracy and speed are insufficient especially for FinFET processes
Solution Approach 1:
The patent segments the capacitance extraction process into multiple stages: (1) decomposing nets into components, (2) classifying component pairs into regular and irregular categories, (3) using pre-calculated libraries for regular cases, and (4) applying equation solvers only for irregular cases. This segmentation enables high accuracy for complex FinFET structures while maintaining fast processing for standard cases.
Solution Approach 2:
The patent performs preliminary actions by pre-calculating and storing capacitance values for regular component pairs in a library before the actual extraction process. During extraction, these pre-calculated values are retrieved directly rather than computing them in real-time, significantly improving speed for common cases while maintaining accuracy for all cases through selective equation solving for irregular configurations.
2Measurement precision
If comprehensive methods are used to handle all layout types, then accuracy improves, but processing time increases
Solution Approach 1:
The patent applies local quality by treating different component pairs differently based on their geometric characteristics. Regular component pairs (with standard dimensions and spacing) use fast library lookup, while irregular component pairs (with non-standard geometries, especially in FinFET processes) use comprehensive equation solving. This localized approach ensures high accuracy where needed without wasting time on cases where simple lookup suffices.
Solution Approach 2:
The patent changes the extraction method based on geometric parameters of component pairs. By analyzing parameters such as component dimensions, spacing, and configuration, the system dynamically selects between library lookup (for regular parameters) and equation solving (for irregular parameters). This parameter-driven selection optimizes the balance between accuracy and processing time.
Data Source
AI summary
The method for extracting a capacitance from a layout is disclosed. The method decomposes a first net into a first and a second component, and decomposes a second net into a third and a fourth component. The method may obtain a first capacitance for the first component and the third component by a first method, and obtain a second capacitance for the second component and the fourth component by a second method different from the first method. A library with a plurality of entries may be provided, wherein each entry has a component pair comprising a component of the first net and a component of the second net, and a pre-calculated capacitance for the component pair. The first method may be to search a library to find a pre-calculated capacitance. The second method may be to obtain the first capacitance by an equation solver on the fly.