Capacitance Measurement Circuit Parasitic Cancellation
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Solution Overview
Problem
Existing capacitance measurement circuits face challenges in reducing or canceling large parasitic capacitances, which can result in output voltage amplitudes exceeding the input voltage range of analog-to-digital converters (ADCs), preventing normal operation.
Innovation Solution
A capacitance measurement circuit that generates multiple excitation signals with different voltage amplitudes to an external capacitance sensor and internal compensation capacitors, allowing for the reduction or cancellation of parasitic capacitances through the use of out-of-phase excitation signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a variable capacitor is used to reduce parasitic capacitance, then the parasitic capacitance reduction capability is improved, but the ability to handle large parasitic capacitance values deteriorates
Solution Approach 1:
The patent employs multiple variable capacitors with different capacitance values that can be dynamically selected and switched based on the magnitude of parasitic capacitance. This dynamic configuration allows the system to adapt to varying parasitic capacitance levels, resolving the contradiction between precision reduction capability and adaptability to large values.
Solution Approach 2:
The system changes the operating parameters by selecting different variable capacitor values according to the parasitic capacitance magnitude. When parasitic capacitance is small, larger compensation capacitors are used for precise cancellation; when parasitic capacitance is large, smaller capacitors are selected to prevent output voltage saturation, thus resolving the technical contradiction.
2Measurement precision
If a variable capacitor is used to reduce parasitic capacitance, then the parasitic capacitance cancellation is improved, but the output voltage range control deteriorates
Solution Approach 1:
The patent dynamically adjusts the compensation capacitor values based on the detected parasitic capacitance level. This dynamic adaptation ensures that parasitic capacitance is effectively canceled while simultaneously keeping the output voltage within the acceptable range for the ADC, resolving the contradiction between cancellation precision and voltage range control.
Solution Approach 2:
The system uses feedback from the output voltage level to adjust the compensation capacitor selection. When the output voltage approaches saturation, the system automatically selects smaller compensation capacitors to reduce the cancellation effect and maintain proper voltage levels, thus resolving the contradiction between precise cancellation and voltage control.
3Device complexity
If a single excitation signal amplitude is used, then the circuit simplicity is maintained, but the ability to handle different parasitic capacitance levels deteriorates
Solution Approach 1:
The patent implements multiple excitation signal amplitude levels that can be dynamically selected based on the parasitic capacitance magnitude. This dynamic amplitude selection allows the system to maintain effective parasitic capacitance compensation across different signal levels while managing the trade-off with increased circuit complexity through systematic design.
Solution Approach 2:
The excitation signal generation circuit is designed to provide multiple amplitude levels from a single circuit structure, making it universally applicable to different parasitic capacitance scenarios. This multi-functionality resolves the contradiction by enabling the circuit to handle various parasitic capacitance levels without requiring completely separate excitation signal paths.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution effectively reduces or cancels parasitic capacitances, ensuring that the output voltage amplitude of the charge to voltage converter (CVC) remains within the input voltage range of the ADC, allowing for proper operation.
Implementation Method 1
a variable capacitor within the CVC may be utilized to reduce/cancel a parasitic capacitance from a sensing capacitance of a capacitor to be measured
Implementation Method 2
a charge to voltage converter (CVC) therein
Data Source
AI summary
A capacitance measurement circuit includes a charge to voltage converter (CVC) that includes at least one first variable capacitor, an excitation signal generation circuit, a differential amplifier, a first switch circuit, and at least one second variable capacitor, wherein a parasitic capacitance from a sensing capacitance sensed by a capacitance sensor is reduced by the at least one first variable capacitor. The excitation signal generation circuit is arranged to generate and connect a first excitation signal to the capacitance sensor, and generate and connect a second excitation signal to the at least one first variable capacitor, wherein the first excitation signal and the second excitation signal are out-of-phase, and a voltage amplitude of the first excitation signal is different from a voltage amplitude of the second excitation signal. The inverting input terminal of the differential amplifier is arranged to receive the sensing capacitance from the capacitance sensor.