Capacitance Reduction via Shrink Sidewall Deposition and Bread Loaf Pockets
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Solution Overview
Problem
Semiconductor device manufacturing faces challenges in reducing capacitance between wirings, as existing methods do not effectively minimize RC delays and require additional materials like low-k dielectric constants and air gaps, which have limitations in dielectric material choices and process complexity.
Innovation Solution
A method involving the formation of a sacrificial layer over a dielectric layer, etching features, filling with a filler material, shrinking spaces with sidewall deposition, and etching gaps to create pockets, which are then closed using a cyclical bread loaf deposition and shaping process to reduce capacitance between semiconductor device wirings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If air gaps are used to reduce capacitance, then capacitance between wirings is reduced, but dielectric material choices are limited and process complexity increases
Solution Approach 1:
The patent introduces an intermediary material (such as silicon oxide, silicon nitride, or silicon carbide) deposited on the sidewalls of the trenches to replace air gaps. This intermediary material serves as the dielectric between conductive features, eliminating the need for air gaps while maintaining capacitance reduction benefits and enabling broader material selection.
Solution Approach 2:
The patent changes the physical parameter of the dielectric material from gas phase (air gaps) to solid phase (deposited films). By depositing solid dielectric materials on trench sidewalls, the invention transforms the dielectric structure while maintaining the spacing function, thereby expanding material choices beyond air.
2Reliability
If air gaps are used to reduce capacitance, then capacitance between wirings is reduced, but process complexity increases
Solution Approach 1:
The deposited dielectric material acts as an intermediary that simplifies the overall process by eliminating the need for complex air gap formation steps. The intermediary material can be deposited using standard CVD or PECVD processes, integrating smoothly into existing fabrication flows.
Solution Approach 2:
The dielectric material is deposited on the sidewalls before the final conductor fill process. This preliminary action ensures that the capacitance reduction structure is in place before subsequent processing steps, simplifying the overall sequence by avoiding post-processing air gap formation.
3Manufacturing precision
If conventional etching methods are used, then features are formed, but manufacturing precision and control over critical dimensions are limited
Solution Approach 1:
The deposited dielectric material on sidewalls serves as a spacer that defines the critical dimensions of the trenches. This intermediary structure provides precise dimensional control during the etching and fill processes, as the spacer width directly determines the final feature dimensions.
Solution Approach 2:
The patent uses thin film deposition to create precisely controlled dielectric layers on sidewalls. These thin films act as flexible spacers that can be deposited with atomic-level precision, enabling superior critical dimension control compared to conventional etching methods alone.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces capacitance by shrinking spaces and forming pockets, allowing for smaller critical dimensions and more flexible dielectric material choices, thereby improving signal propagation efficiency and reducing RC delays in semiconductor devices.
Implementation Method 1
A plasma processing chamber, comprising a chamber wall forming a plasma processing chamber enclosure, a substrate support for supporting a substrate within the plasma processing chamber enclosure
Implementation Method 2
Widths of the spaces between the parts of the filler material are shrunk with a shrink sidewall deposition
Implementation Method 3
The closing the gap comprises a plurality of cycles, where each cycle comprises a bread loaf deposition phase and a bread loaf profile shaping phase
Data Source
AI summary
A method for reducing capacitances between semiconductor device wirings is provided. A sacrificial layer is formed over a dielectric layer. A plurality of features are etched into the sacrificial layer and dielectric layer. The features are filled with a filler material. The sacrificial layer is removed, so that parts of the filler material remain exposed above a surface of the dielectric layer, where spaces are between the exposed parts of the filler material, where the spaces are in an area formerly occupied by the sacrificial layer. Widths of the spaces between the parts of the filler material are shrunk with a shrink sidewall deposition. Gaps are etched into the dielectric layer through the shrink sidewall deposition. The filler material and shrink sidewall deposition are removed.