On-Die Capacitance Measurement for Resistive Memory Layer Thickness
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Solution Overview
Problem
Variations in semiconductor fabrication processes lead to inconsistencies in memory layer thickness across semiconductor wafers and dies, affecting the performance of two-terminal memory devices, which can result in defective devices and increased production costs due to the need for trim values and quality control challenges.
Innovation Solution
A circuit is integrated on-die to measure parasitic capacitance of resistive switching devices, allowing for accurate and reproducible determination of memory layer thickness, enabling improved quality control and optimization of fabrication processes by selectively connecting to different groups of two-terminal resistive switching devices and providing multiple circuits to assess memory layer uniformity across a wafer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional fabrication processes are used without on-die capacitance measurement, then manufacturing simplicity is maintained, but manufacturing precision deteriorates due to uncontrolled memory layer thickness variations
Solution Approach 1:
The patent applies preliminary action by measuring the parasitic capacitance of the memory layer during the fabrication process itself, before the devices are fully assembled and tested. This on-die capacitance measurement allows the thickness of the memory layer to be determined and controlled early in the manufacturing process, enabling real-time adjustments to be made while the wafer is still being processed, thus improving manufacturing precision without significantly increasing overall process complexity
Solution Approach 2:
The patent replaces mechanical measurement methods (such as physical cross-sectioning or external probing) with an electrical measurement approach. By measuring the parasitic capacitance of the memory layer through electrical connections already present on the die, the system substitutes a simple electrical RC time constant measurement for complex mechanical thickness measurement techniques, thereby improving precision while maintaining fabrication simplicity
2Manufacturing precision
If multiple circuits are added to assess memory layer uniformity across the wafer, then manufacturing precision improves, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the wafer into multiple regions and placing measurement circuits at different locations across the wafer. Each circuit measures the parasitic capacitance of the memory layer in its local region, allowing the uniformity of the memory layer to be assessed across the entire wafer. This segmented approach enables comprehensive quality control without requiring a single complex centralized measurement system
Solution Approach 2:
The measurement circuits are integrated directly into the fabrication process and use the existing memory layer structures themselves as the measurement objects. The parasitic capacitance of the memory layer is measured in-situ without requiring separate test structures or additional processing steps, allowing the memory layer to serve both its functional purpose and its measurement purpose simultaneously
3Reliability
If process variations are not monitored and controlled, then manufacturing simplicity is maintained, but reliability deteriorates due to performance variations and defective parts
Solution Approach 1:
The patent implements feedback by measuring the parasitic capacitance of the memory layer during fabrication and using this information to adjust subsequent processing steps. The measured capacitance values provide real-time feedback on memory layer thickness and uniformity, allowing process parameters to be adjusted to compensate for variations and ensure that devices meet performance specifications, thereby improving reliability without excessive production overhead
Solution Approach 2:
The patent uses parameter changes by monitoring the parasitic capacitance value as an indicator of memory layer thickness and adjusting fabrication parameters accordingly. By tracking changes in the capacitance parameter during the manufacturing process, the system can identify deviations from specifications and modify processing conditions to correct these deviations, ensuring consistent device performance and reducing the number of defective parts
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables precise measurement of memory layer thickness, improving the quality control of semiconductor devices, reducing defective parts, and optimizing fabrication costs by allowing for real-time adjustments of trim values and identifying uniformity across the wafer, thereby enhancing the overall performance and yield of memory structures.
Implementation Method 1
determine a parasitic capacitance of the two-terminal memory devices
Implementation Method 2
output a frequency determined by an RC circuit comprising the operational amplifier and the resistor
Data Source
AI summary
A semiconductor device includes two-terminal memory devices characterized by a range of program voltages and a first capacitance, wherein the two-terminal memory devices are coupled in parallel between ground and a first common node, a first capacitor having a second capacitance, coupled between ground and a second common node, a voltage source configured to provide an input voltage lower than the range of program voltages, a first operational amplifier including an inverting input, a non-inverting input, and an output, wherein the non-inverting input is coupled to the first voltage source, wherein the inverting input is coupled to a third common node, and wherein the output is coupled to a fourth common node, a first resistance device coupled between the third common node and the fourth common node, and wherein the first common node is coupled to the second common node and the third common node.