Integrated Capacitance Sensing Module with Embedded Memory
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Solution Overview
Problem
The existing fingerprint recognition systems require separate fabrication processes for capacitance sensors and memory components, leading to increased complexity and size due to the incompatibility of logic circuit processes with floating gate transistor manufacturing.
Innovation Solution
An integrated capacitance sensing module is developed, where a capacitor sensor and memory are constructed on the same substrate using a single poly floating gate transistor process, compatible with current logic circuit processes, enabling the fabrication of both components simultaneously.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If separate fabrication processes are used for capacitance sensors and memory components, then each component can be manufactured with its own optimized process, but the overall system complexity and size increase
Solution Approach 1:
The patent merges the capacitance sensor and memory components into a single integrated module that uses a unified fabrication process. The sensing electrode, insulation layer, and memory structure are formed simultaneously in the same manufacturing sequence, eliminating the need for separate fabrication processes while maintaining component quality through process integration.
2Ease of manufacture
If separate fabrication processes are used for capacitance sensors and memory components, then each component can be manufactured independently, but the overall system size increases
Solution Approach 1:
The patent implements a nested structure where the memory component is integrated within the capacitance sensing module. The memory structure is formed between the sensing electrode and the substrate, utilizing the same vertical space and reducing the horizontal footprint. This nesting approach allows independent manufacturing capabilities to be preserved while minimizing overall system area.
3Reliability
If floating gate transistor process is used for memory, then nonvolatile storage is achieved, but compatibility with current logic circuit processes is lost
Solution Approach 1:
The patent modifies the fabrication process parameters to achieve compatibility between the floating gate transistor process and current logic circuit manufacturing. By adjusting process conditions such as temperature, deposition methods, and material layers, the patent enables the memory component to use floating gate transistors for nonvolatile storage while maintaining compatibility with standard logic circuit fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a compact system with reduced size and improved manufacturing efficiency, as the memory is embedded within the capacitance sensing module, enhancing the integration and functionality of fingerprint recognition systems.
Implementation Method 1
the sensing circuit realizes the changes of the capacitance values of the plural capacitors according to a change of the electric field of the sensing region
Implementation Method 2
According to a change of the electric field of the sensing region 122, a sensing circuit (not shown) of the capacitance sensor 102 realizes the changes of the capacitance values
Data Source
Figure 1
Figure 2A~2C
Figure 3A~3D
AI summary
An integrated capacitance sensing module includes a silicon substrate, a first and a second and a third interlayer dielectric layers, plural conducting layers, a shielding layer, a lower and a upper sensing electrode layers, a protective coating layer. An embedded memory and a sensing circuit are constructed in the silicon substrate. The first interlayer dielectric layer covers the silicon substrate. The plural conducting layers are formed over the first interlayer dielectric layer. The shielding layer is formed over the plural conducting layers. The second interlayer dielectric layer covers the shielding layer. The lower sensing electrode layer is formed over the second interlayer dielectric layer. The third interlayer dielectric layer is formed over the lower sensing electrode layer. The upper sensing electrode layer is formed over the third interlayer dielectric layer. The protective coating layer covers the upper sensing electrode layer.