Capacitance-to-Voltage Conversion Circuit Noise Reduction
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Solution Overview
Problem
Capacitance-to-voltage conversion circuits in capacitive sensors face challenges in reducing device noise while maintaining processing time and minimizing power consumption, as existing methods to limit bandwidth increase processing time and power consumption.
Innovation Solution
The circuit employs a second sample and hold circuit that performs simultaneous sampling with the first sample and hold circuit during an initial period and subsequent sampling during the rear-end period, increasing the load capacity and narrowing the bandwidth to reduce high-order device noises, while allowing the second sample and hold circuit to connect only during the rear-end period to reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If bandwidth limitation is performed by connecting a capacitance element to the output terminal of the differential amplifier, then high-order frequency device noise is suppressed, but processing time increases and power consumption increases
Solution Approach 1:
The second sample and hold circuit performs preliminary sampling of the output voltage during the initial sampling period, storing the sampled voltage in its holding capacitance. This preliminary action allows the circuit to have charge accumulation ready before the rear-end period, avoiding the need for continuous bandwidth limitation and reducing both processing time and power consumption while maintaining noise suppression capability
Solution Approach 2:
The circuit operates in periodic cycles with distinct phases: during the initial sampling period, the second sample and hold circuit samples and holds the output voltage; during the rear-end period, it performs subsequent sampling. This periodic operation allows bandwidth limitation to be applied intermittently rather than continuously, reducing average power consumption and processing time while still suppressing high-order frequency device noise when needed
2Object-affected harmful factors
If bandwidth limitation is performed by connecting a capacitance element to the output terminal of the differential amplifier, then high-order frequency device noise is suppressed, but power consumption increases
Solution Approach 1:
The second sample and hold circuit performs preliminary sampling during the initial sampling period, accumulating charge in its holding capacitance before the rear-end period. This preliminary charge accumulation allows the circuit to operate with reduced bandwidth limitation during non-critical periods, thereby reducing power consumption while maintaining noise suppression capability when required
Solution Approach 2:
The circuit applies bandwidth limitation periodically rather than continuously - during the initial sampling period when the second sample and hold circuit is sampling, and during the rear-end period when subsequent sampling occurs. This periodic application of bandwidth limitation reduces average power consumption compared to continuous bandwidth limitation, while still effectively suppressing high-order frequency device noise during critical sampling intervals
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces high-order device noises while maintaining processing time and reducing power consumption, achieving noise reduction without increasing the time required to accumulate electric charges.
Implementation Method 1
an integration circuit that outputs an output voltage as a result of integration of electric charges supplied from the variable capacitance element
Implementation Method 2
a first sample and hold circuit that samples and holds the output voltage outputted from the integration circuit
Data Source
AI summary
A capacitance-to-voltage conversion circuit including a variable capacitance element, an integration circuit, and first and second sample and hold circuits. Capacitance value of the variable capacitance element varies depending on a physical quantity. The integration circuit outputs a voltage as a result of integration. The first sample and hold circuit samples and holds the voltage. The second sample and hold circuit samples and holds the sampled voltage and performs a simultaneous sampling operation in synchronism with the first sample and hold circuit at the same period as at least an initial sampling period. The second sample and hold circuit performs a sampling operation at a rear-end period in a sampling period of the first sample and hold circuit other than the sampling period.