Capacitance Sensing Wafer Layout for Non-Contact Thickness Metrology
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Solution Overview
Problem
Conventional wafer metrology methods for measuring thickness and inspecting voids in semiconductor wafers often require physical contact, which can damage the wafer surface and are not suitable for opaque or highly reflective materials, leading to inaccurate measurements and potential deformation.
Innovation Solution
A non-contact capacitance sensing array wafer system that measures capacitance between a capacitance sensing array wafer and a testing semiconductor wafer to determine thickness and detect defects, using a group of capacitance sensing units aligned in various patterns and adjustable voltage differences for sensitivity, with optional inductance sensing for additional measurements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If physical contact methods (probe or stylus) are used for wafer thickness measurement and void inspection, then measurement precision can be achieved, but the wafer surface may be damaged and measurement reliability decreases
Solution Approach 1:
The patent replaces mechanical contact-based measurement systems with a non-contact capacitance sensing system. The capacitance sensing array wafer measures thickness and detects voids through electrical field interactions without physical contact, thereby eliminating mechanical damage to the wafer surface while maintaining measurement precision.
Solution Approach 2:
The patent introduces an intermediate measurement mechanism using capacitance sensing units that measure the electrical field between the sensing array and the wafer. This intermediary electrical field measurement allows thickness and void detection without direct mechanical contact, preventing surface damage.
2Adaptability or versatility
If conventional contact-based metrology methods are used, then measurement capability is achieved, but the system is not suitable for opaque or highly reflective materials leading to inaccurate measurements
Solution Approach 1:
The patent changes the measurement parameter from optical properties (which fail for opaque materials) to electrical capacitance properties. The capacitance sensing units measure the electrical field interaction, which is independent of the wafer's optical characteristics, enabling accurate measurement of both transparent and opaque materials including highly reflective ones.
3Measurement precision
If physical contact measurement is used to ensure precise thickness measurement, then measurement precision is improved, but the wafer may deform and yield decreases
Solution Approach 1:
The patent replaces mechanical contact measurement with non-contact capacitance sensing, eliminating the mechanical force that causes wafer deformation. This substitution maintains measurement precision while preserving wafer integrity and improving device yield.
Solution Approach 2:
The patent prevents potential damage before it occurs by using a non-contact measurement system. The capacitance sensing array wafer interacts with the test wafer through electrical fields only, providing a cushioning effect that prevents mechanical stress and deformation from ever occurring during measurement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables high-resolution, non-destructive measurement of wafer thickness and void detection, providing precise and reliable results without surface damage, suitable for both transparent and opaque materials.
Implementation Method 1
measuring a capacitance between the capacitance sensing array wafer and the testing semiconductor wafer
Data Source
AI summary
A capacitance sensing device including a semiconductor wafer having a frontside surface and a backside surface, a plurality of capacitance sensing units disposed close to the frontside surface of the semiconductor wafer, a plurality of first electrodes disposed on the backside surface of the semiconductor wafer, each of the plurality of the first electrodes being aligned to corresponding capacitance sensing unit of the plurality of capacitance sensing units, a first plurality of electrical interconnections connecting each of the plurality of capacitance sensing units to a signal processing circuitry, and a second plurality of electrical interconnections connecting each of the plurality of first electrodes to a power source.


