Capacitance Wiring Line Width Control for Display Device Etching Shift
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Solution Overview
Problem
In organic EL display devices, etching shifts during the formation of upper electrodes can lead to reduced capacitance in subpixels, causing display unevenness due to variations in the overlap area between upper and lower electrodes.
Innovation Solution
A display device structure is implemented where the capacitance wiring line is electrically connected to the capacitance electrode and gate electrode, with the line width of the capacitance wiring line equal to or greater than the capacitance electrode and less than the gate electrode, ensuring consistent capacitance by maintaining the designed overlap area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If etching is used to pattern the upper electrode (capacitance electrode), then the electrode can be formed, but etching shift occurs causing line width variation and capacitance change
Solution Approach 1:
The patent transitions from a single-layer electrode structure to a multi-layer structure by adding a third metal layer (capacitance wiring line) above the capacitance electrode. This dimensional addition allows the capacitance wiring line to extend beyond the capacitance electrode boundaries, compensating for etching shifts and ensuring the capacitance forming region maintains the intended overlap area with the gate electrode.
Solution Approach 2:
The patent modifies the geometric parameters of the capacitance wiring line, specifically setting its line width to be equal to or greater than the capacitance electrode line width. This parameter change ensures that even when etching shifts occur, the capacitance wiring line maintains sufficient overlap with the gate electrode, thereby stabilizing the capacitance value.
2Ease of manufacture
If capacitance electrode line width is reduced due to etching shift, then manufacturing is simplified, but capacitance decreases causing display unevenness
Solution Approach 1:
By adding the capacitance wiring line as a third metal layer extending beyond the capacitance electrode, the patent creates a redundant capacitance forming region. This ensures that even if the capacitance electrode line width is reduced due to etching shifts, the overall capacitance is maintained through the extended wiring line overlap with the gate electrode.
Solution Approach 2:
The capacitance wiring line is designed with extended dimensions beforehand to compensate for potential etching shifts. This pre-compensation strategy ensures that the capacitance value remains stable even when manufacturing variations occur, effectively cushioning against capacitance degradation.
3Adaptability or versatility
If the capacitance electrode line width varies, then manufacturing flexibility increases, but display uniformity deteriorates due to capacitance variation
Solution Approach 1:
The patent adds the capacitance wiring line dimension that extends beyond the capacitance electrode in plan view. This additional dimensional element creates a buffer zone that absorbs line width variations, ensuring that the capacitance forming region (overlap between gate electrode and capacitance structure) remains consistent despite manufacturing tolerances.
Solution Approach 2:
The patent specifies that the capacitance wiring line width should be equal to or greater than the capacitance electrode line width. This parameter relationship ensures that variations in capacitance electrode width do not directly translate to capacitance value variations, as the extended wiring line maintains the necessary overlap area with the gate electrode.
Data Source
AI summary
A capacitor (9ha) includes a gate electrode (14a), a first interlayer insulating film (15), a capacitance electrode (16c), and a capacitance wiring line (18ha). The capacitance wiring line (18ha) is electrically connected to the capacitance electrode (16c). A capacitance of the capacitor (9ha) is formed between the gate electrode (14a) and the capacitance electrode (16c) and the capacitance wiring line (18ha) arranged facing each other across the first interlayer insulating film (15). A line width (W18h) of the capacitance wiring line (18ha) is equal to or greater than a line width (W16c) of the capacitance electrode (16c) and equal to or less than a line width (W14a) of the gate electrode (14a).