Wafer-Level Integration of Capacitive Micro-Accelerometer and CMOS Circuitry
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Solution Overview
Problem
Capacitive micro-accelerometers face challenges in achieving large mechanical sensitivity and integrating with CMOS circuitry to reduce input parasitics and improve signal-to-noise ratio, while also requiring cost-effective manufacturing and packaging for mass-volume applications.
Innovation Solution
A micromachined sensor process involving the formation of a sensing structure and circuitry on separate wafers, with a capacitive sensing structure featuring conductive layers and a buried insulator layer, allowing for vertical integration and the creation of a symmetric capacitive full-bridge structure, which reduces parasitics and enhances sensitivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If capacitive micro-accelerometers use a wafer-thick large proof mass to achieve high sensitivity, then mechanical sensitivity is improved, but device complexity and packaging difficulty increase
Solution Approach 1:
The device is divided into two separate wafers: a first wafer containing the sensing structure with proof mass, and a second wafer containing the CMOS circuitry. This segmentation allows each wafer to be optimized independently - the first wafer can have a thick proof mass for high sensitivity while the second wafer handles circuit functions, reducing overall device complexity and packaging difficulty.
Solution Approach 2:
The patent transitions from a monolithic planar structure to a three-dimensional vertically stacked configuration. By bonding the first wafer (sensing structure) to the second wafer (circuitry) in the vertical dimension, the patent achieves high sensitivity through thick proof mass while managing complexity through spatial separation of sensing and circuit functions.
2Adaptability or versatility
If capacitive micro-accelerometers are hybrid packaged with interface circuitry, then integration is achieved, but input parasitics increase and signal-to-noise ratio deteriorates
Solution Approach 1:
The patent segments the device into a sensing wafer and a circuit wafer that are separately fabricated and then bonded together. This segmentation allows the sensing structure to be optimized for sensitivity with minimal parasitic capacitance, while the circuitry is integrated through wafer bonding, achieving both integration capability and low parasitics for improved signal-to-noise ratio.
Solution Approach 2:
The patent uses wafer bonding as an intermediary technique to connect the sensing structure and circuitry. This bonding interface provides electrical connection while maintaining mechanical stability, achieving integration without the high parasitics associated with traditional hybrid packaging methods.
3Ease of manufacture
If surface micromachining is used to fabricate accelerometers on a single silicon wafer, then manufacturing simplicity is improved, but proof mass size is limited and mechanical noise floor increases
Solution Approach 1:
The patent divides the fabrication process into two separate wafer processes that are subsequently bonded. The first wafer is processed to create the sensing structure with a thick proof mass for low mechanical noise floor, while the second wafer contains the circuitry. This segmentation overcomes the single-wafer size limitations while maintaining manufacturing simplicity through standard wafer-level processes.
Solution Approach 2:
The patent creates a composite structure by bonding two different wafers together - one optimized for mechanical sensing with thick proof mass and another for electronics. This composite approach combines the advantages of both separate structures, achieving low mechanical noise floor while maintaining ease of manufacture through wafer-level fabrication.
4Measurement precision
If large capacitive sensitivity is used to compensate for high electrical noise floor, then signal detection capability is improved, but mechanical sensitivity requirements become more stringent
Solution Approach 1:
The patent segments the device into sensing and circuit portions on separate wafers, allowing the sensing structure to be optimized for mechanical sensitivity with a thick proof mass. This segmentation enables simultaneous optimization of both mechanical sensitivity (for low noise floor) and capacitive sensitivity (for signal detection), eliminating the need to use large capacitive sensitivity as a compensation mechanism.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables high capacitive sensitivity and low mechanical noise floor, simplifies packaging, and reduces manufacturing costs, achieving improved signal-to-noise ratio and cost-effectiveness for mass-volume applications.
Implementation Method 1
capacitive sensing structure that includes a member comprising first and second conductive layers and a buried insulator layer separating the first and second conductive layers
Implementation Method 2
buried insulator layer separating the first and second conductive layers
Data Source
AI summary
A micromachined sensor and a process for fabrication and vertical integration of a sensor and circuitry at wafer-level. The process entails processing a first wafer to incompletely define a sensing structure in a first surface thereof, processing a second wafer to define circuitry on a surface thereof, bonding the first and second wafers together, and then etching the first wafer to complete the sensing structure, including the release of a member relative to the second wafer. The first wafer is preferably a silicon-on-insulator (SOI) wafer, and the sensing structure preferably includes a member containing conductive and insulator layers of the SOI wafer. Sets of capacitively coupled elements are preferably formed from a first of the conductive layers to define a symmetric capacitive full-bridge structure.