Capacitive ADC for CMOS Image Sensors With Accurate Weighted Pixel Summing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing CMOS-type solid-state image pickup apparatuses face errors in dynamic range expansion due to noise and response lag during pixel signal amplification and A/D conversion, leading to inaccuracies in weighting addition of pixel signals.
Innovation Solution
An A/D conversion circuit with capacitive elements that hold and synthesize pixel signals, generating a node potential for digital value generation, and a signal synthesis unit that temporarily holds and amplifies pixel signals to perform weighting addition without errors from amplification or conversion processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If pixel signals are amplified and converted to digital values by an A/D conversion circuit, then the signals can be processed and stored for weighting addition, but conversion errors and noise-related inaccuracies are introduced
Solution Approach 1:
The patent applies preliminary action by performing weighting addition on pixel signals in the analog domain before A/D conversion. The weighting addition circuit synthesizes multiple pixel signals (e.g., Sig1, Sig2, Sig3) with appropriate weights (e.g., 1:2:1) while they are still analog voltages, and only then converts the resulting analog signal to digital. This prevents conversion errors and quantization noise from being introduced at multiple separate conversion steps, thereby maintaining signal accuracy while still enabling full digital processing capabilities.
2Measurement precision
If multiple pixel signals are held and synthesized using capacitive elements, then weighting addition can be performed without conversion errors, but the device complexity increases
Solution Approach 1:
The patent merges the weighting addition function with the existing A/D conversion circuitry by integrating a weighting addition circuit that uses capacitive elements (such as holding capacitors and synthesis capacitors) directly within the conversion path. Instead of adding a completely separate analog processing stage, the weighting addition is combined with the signal holding and conversion functions, sharing common circuit elements and control logic. This reduces the overall device complexity while maintaining high weighting addition accuracy.
3Loss of information
If pixel signals are converted to digital values before weighting addition, then digital processing and memory storage are enabled, but noise and conversion errors degrade the dynamic range expansion
Solution Approach 1:
The patent performs weighting addition on analog pixel signals before A/D conversion, preserving the full dynamic range of the original signals throughout the weighting process. By synthesizing weighted sums of multiple pixel signals (e.g., expanding dynamic range through central pixel and surrounding pixel combination) in the analog domain, the patent avoids introducing quantization errors and conversion noise that would limit dynamic range expansion. Only after the weighted synthesis is complete is the analog signal converted to digital, ensuring maximum information preservation and reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables accurate weighting addition of pixel signals without conversion errors or noise-related inaccuracies, improving the dynamic range expansion in CMOS-type solid-state image pickup apparatuses.
Implementation Method 1
A/D conversion circuit with capacitive elements that hold and synthesize pixel signals
Data Source
AI summary
Provided is an ADC in which a plurality of pixel signals input through a vertical signal line of a solid-state image pickup apparatus are held in advance using some capacitors among a plurality of capacitors within the ADC. A potential of a node is generated by the respective pixel signals held in the capacitors. Thereafter, the potential of the node is changed by changing the voltages of counter electrodes of the capacitors, and the digital values of the pixel signals are generated by comparing the potential of the node with a predetermined potential.