Capacitive ADC Switching Architecture for Higher Precision
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Solution Overview
Problem
Existing capacitive analog-to-digital converters in handheld devices face challenges in achieving high accuracy and fast conversion speed while maintaining low power consumption, particularly in image processing and biomedicine applications.
Innovation Solution
A capacitive analog-to-digital converter design that includes multiple capacitor banks and switches, controlled by a successive approximation logic controller, allowing for precise voltage comparisons and improved accuracy through differential operation modes, reducing power consumption by eliminating the need for resistor string voltage dividers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional capacitor arrays with N capacitors for N-bit conversion are used, then the device complexity is low, but the measurement precision is insufficient
Solution Approach 1:
The patent divides the capacitor array into N capacitor banks, where each bank contains multiple capacitors (totaling M capacitors where M > N). This segmentation allows the system to achieve higher measurement precision by using more capacitors than the minimum required for N-bit conversion, while maintaining a structured and manageable architecture through the bank organization.
2Measurement precision
If resistor string voltage dividers are used for voltage comparison, then the measurement precision can be improved, but the use of energy increases significantly
Solution Approach 1:
The patent replaces the traditional resistor string voltage divider mechanism with a capacitor-based voltage comparison system. By using capacitors to store and compare voltage levels directly, the system achieves accurate voltage comparison without the continuous power consumption associated with resistor-based voltage division, thereby significantly reducing overall power consumption.
3Productivity
If the conversion speed is increased to meet real-time processing requirements, then the productivity is improved, but the measurement precision deteriorates due to reduced conversion time
Solution Approach 1:
The patent employs a successive approximation logic controller that systematically controls the switching of capacitors in a predetermined sequence. This preliminary structured approach allows the conversion process to proceed efficiently through multiple stages, achieving both fast conversion speed and high precision by pre-planning the capacitor switching sequence rather than performing random or unstructured comparisons.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the accuracy of analog-to-digital conversion by 0.8 bits compared to traditional 4-bit converters, achieving a resolution of 4.8 bits while minimizing power consumption, thus meeting the demands of high-resolution and low-power requirements in modern devices.
Implementation Method 1
the comparator is configured to: compare a magnitude of voltage received at the first input with a magnitude of voltage received at the second input, and output N comparison results respectively corresponding to N bits of binary codes
Implementation Method 2
a first capacitor array, including N first capacitor banks that include M first capacitors
Data Source
AI summary
A capacitive analog-to-digital converter, an analog-to-digital conversion system, a chip, and a device. The capacitive analog-to-digital converter includes: a first capacitor array, including N first capacitor banks that include M first capacitors, where M is a positive integer greater than N; M first switches, respectively connected to first electrode plates of the M first capacitors in a one-to-one correspondence to enable a successive approximation logic controller to control connections of the first electrode plates of the M first capacitors with an output of a voltage generation circuit and with a first sampling voltage output by controlling the M first switches; a comparator, including a first input, a second input and an output; and the successive approximation logic controller, connected to the output of the comparator, and configured to control the M first switches according to comparison results output by the output of the comparator.