Capacitive Cancellation for Far End Noise in Multi-Layer Ceramic Packages
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Solution Overview
Problem
Multi-layer ceramic packages experience significant far end noise due to inductive cross-talk between signal lines, which limits signaling rates and performance, and existing technologies have not effectively addressed this issue without increasing costs or incurring wire channel penalties.
Innovation Solution
The introduction of signal line offsets in multi-layer ceramic packages, where vias are removed or not present, allows for capacitive cross-talk to negate inductive cross-talk, reducing far end noise by extending signal lines into areas without ground lines, thereby introducing opposite-polarity capacitive interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If signal lines are arranged in a stacked tri-plate configuration with meshed reference planes, then controlled impedance environment is achieved for high speed signal propagation, but inductive cross-talk between signal lines causes significant far end noise
Solution Approach 1:
The patent applies preliminary anti-action by introducing capacitive coupling structures (offset signal lines) that generate capacitive cross-talk in advance to counteract the harmful inductive cross-talk. The offset signal lines are positioned to create capacitive coupling between adjacent signal lines, producing a capacitive noise component that opposes and reduces the far end inductive noise from simultaneous switching events.
Solution Approach 2:
The patent converts the harmful inductive cross-talk into a benefit by deliberately introducing capacitive cross-talk through offset signal line positioning. The capacitive coupling between offset signal lines generates a noise component with opposite polarity to the inductive noise, effectively using one type of electromagnetic coupling to cancel another, thereby reducing far end noise while maintaining high speed signal propagation.
2Object-affected harmful factors
If vias are removed to allow signal line offsets, then capacitive cross-talk is introduced to reduce inductive cross-talk, but signal line length is increased
Solution Approach 1:
The patent applies dimensionality change by transitioning from a planar signal line arrangement to a three-dimensional offset configuration. Signal lines are positioned at different lateral offsets in adjacent layers, creating capacitive coupling through vertical and lateral separation. This spatial reconfiguration introduces capacitive cross-talk without requiring significant additional signal line length, as the offset positioning in the lateral dimension achieves the desired capacitive effect.
3Object-affected harmful factors
If offset signal lines are used to reduce far end noise, then capacitive cancellation is achieved, but package complexity increases
Solution Approach 1:
The patent applies local quality by implementing offset signal line positioning only in specific regions where far end noise is most problematic, rather than uniformly across the entire package. The offset configuration is selectively applied to signal lines experiencing significant inductive cross-talk, while other areas maintain the conventional stacked tri-plate structure. This localized approach reduces far end noise without unnecessarily increasing overall package complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces far end noise, achieving a 0-37.2% reduction in noise levels, thereby enhancing signal integrity and increasing maximum signaling rates and performance without increasing package costs or incurring wire channel penalties.
Implementation Method 1
Because these offsets of the signal lines exist in parallel planes above or below each other, with no ground lines existing directly between these signal line offsets, a capacitive cross-talk is introduced into the signal lines.
Implementation Method 2
The noise is caused by a high number of simultaneously switching off-chip drivers (OCD noise) and by a high number of simultaneously switching latches and the associated logic gates (logic noise). Both noise sources generate noise due to line-to-line coupling and due to the collapse of the voltage-ground (GND) system.
Data Source
AI summary
A mechanism for reducing the vertical cross-talk interference experienced in signal lines due to the inductive affects from signal lines in other signal planes of a multi-layer ceramic package is provided. With the apparatus and method, one or more vias in the multi-layer ceramic package may be removed from the structure to provide area through which an offset of the signal lines may pass. Because these offsets of the signal lines exist in parallel planes above or below each other, with no ground lines existing directly between these signal line offsets, a capacitive cross-talk is introduced into the signal lines. This capacitive cross-talk is opposite in polarity to the inductive cross-talk already experienced by the signal lines. As a result, the capacitive cross-talk tends to negate or reduce the inductive cross-talk thereby reducing the far end noise in the signal line.