Capacitive Chip for Multi-Chip Module Noise Filtering
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Solution Overview
Problem
Multi-chip modules face challenges in providing sufficient capacitance due to physical limitations of die surface areas and the size constraints of traditional decoupling capacitors, which can lead to inadequate noise reduction and signal integrity issues at higher frequencies and lower power supply voltages.
Innovation Solution
A capacitive chip with distributed capacitive units and vias, configured to provide adjustable capacitance and resistance, is integrated into a multi-chip module, allowing for enhanced power delivery and noise immunity by decoupling noise from power supply voltages and enabling real-time adjustment of capacitance based on signal characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If traditional decoupling capacitors (MIM or MOSCAPs) are used on dies, then high frequency signals can be filtered from power supply voltages, but the desired sizes of these capacitors are too large to be located anywhere but the uppermost position of a die stack
Solution Approach 1:
The patent transitions from planar capacitor layouts to three-dimensional stacked capacitor structures. Multiple capacitor banks are arranged in vertical stacks across multiple dies, utilizing the third dimension (height/stacking direction) to achieve the required capacitance without increasing the lateral footprint on any single die. This allows capacitors to be distributed throughout the stack rather than confined to the uppermost position only.
Solution Approach 2:
The total capacitance requirement is divided into multiple smaller capacitor banks distributed across different dies in the stack. Instead of using one or two large capacitors on a single die, the patent segments the capacitance into numerous smaller units spread throughout the multi-chip module, with each die contributing a portion of the total capacitance.
2Area of stationary object
If capacitor size is reduced to fit within die surface area constraints, then capacitors can be positioned at multiple locations in the die stack, but the capacitance provided may still be insufficient for desirable noise reduction
Solution Approach 1:
The patent combines the capacitance contributions from multiple distributed capacitor banks across several dies to achieve the total required capacitance. By merging these smaller individual capacitances in parallel through the interconnect structure, the system achieves sufficient overall capacitance for effective noise filtering while maintaining compact die dimensions.
Solution Approach 2:
The solution uses vertical stacking to multiply the effective capacitance density. By arranging capacitor banks in three-dimensional space across multiple dies rather than spreading them laterally, the system achieves high total capacitance within a compact volume, providing adequate noise immunity without excessive die surface area usage.
3Reliability
If more capacitance is provided to improve noise filtering, then signal integrity improves, but the physical space required for capacitors increases
Solution Approach 1:
The patent exploits the vertical dimension in multi-chip stacking to accommodate larger total capacitance without proportionally increasing the lateral footprint. By distributing capacitor banks vertically across multiple dies and utilizing the stacking height, the system achieves high capacitance values needed for signal integrity while maintaining a compact overall module volume.
Solution Approach 2:
The capacitance is segmented into multiple small distributed units throughout the stack, allowing the total capacitance to be accumulated through parallel combination of these segments. This segmentation approach enables high overall capacitance for improved signal integrity while keeping individual capacitor sizes small and efficiently utilizing the available three-dimensional space.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively increases operating margins and noise immunity by providing sufficient capacitance and flexible power supply voltage configurations, enabling continued operation even without external power and improving overall signal integrity in multi-chip modules.
Implementation Method 1
A capacitive chip with distributed capacitive units and vias, configured to provide adjustable capacitance and resistance
Data Source
AI summary
Apparatuses, multi-chip modules, capacitive chips, and methods of providing capacitance to a power supply voltage in a multi-chip module are disclosed. In an example multi-chip module, a signal distribution component may be configured to provide a power supply voltage. A capacitive chip may be coupled to the signal distribution component and include a plurality of capacitive units. The capacitive chip may be configured to provide a capacitance to the power supply voltage. The plurality of capacitive units may be formed from memory cell capacitors.