Capacitive CMOS Transistor Testing Without Contact
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Solution Overview
Problem
Current methods for testing CMOS transistors on semiconductor wafers do not effectively detect failures before dicing, leading to costly assembly issues and inefficient testing processes.
Innovation Solution
A method involving an electrical testing unit with a support plate and a metal layer for capacitive coupling with CMOS transistors, allowing for the application of a drive potential to test the transistor's function without direct contact, enabling early detection of failures and reducing testing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional electrical testing methods are used on semiconductor wafers, then testing can be performed, but failures cannot be detected before dicing leading to costly assembly issues
Solution Approach 1:
The patent replaces direct electrical contact testing with capacitive coupling testing. A metal layer is positioned above the semiconductor wafer to form a capacitor with the control contact, allowing electrical testing without physical contact. This substitution enables effective failure detection before dicing while maintaining testing efficiency.
Solution Approach 2:
The patent introduces a metal layer as an intermediary between the testing system and the CMOS transistor control contact. This metal layer serves as a capacitor plate that couples electrically to the control contact through capacitance, enabling indirect electrical testing that detects failures before dicing without requiring direct contact.
2Ease of operation
If direct electrical contact is used to apply voltage to the control terminal, then the transistor can be tested, but contact with the open control terminal is difficult to establish
Solution Approach 1:
The patent replaces mechanical contact with capacitive coupling. Instead of physically contacting the open control terminal with a probe, a metal layer is positioned above the wafer to form a capacitor with the control contact. Voltage is applied through this capacitive coupling, eliminating the need for direct mechanical contact and simplifying the testing operation.
Solution Approach 2:
The metal layer acts as an intermediary that bridges the gap between the testing system and the control terminal. By forming a capacitor with the control contact, it enables voltage application without direct contact, making the testing process easier while avoiding the complexity of establishing reliable mechanical contact with open terminals.
3Measurement precision
If multiple measured values are taken to ensure reliable testing, then accuracy improves, but measuring time increases
Solution Approach 1:
The patent varies the drive potential applied to the metal layer to obtain a characteristic of the electrical variable. By measuring how the electrical response changes with different drive potentials, reliable conclusions about transistor function can be drawn from a limited set of measurements, achieving both accuracy and speed.
Solution Approach 2:
The patent determines that a limited number of measured values at different drive potentials are sufficient to reliably test CMOS transistor function. This partial action approach achieves adequate testing reliability without requiring exhaustive measurements, thereby maintaining high testing productivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables reliable and cost-effective testing of CMOS transistors before dicing, allowing for the detection of failures and determination of leakage currents and channel resistance with minimal measured values and short measuring time.
Implementation Method 1
the control contact is capacitively coupled by applying a drive potential to the metal layer
Data Source
AI summary
A method for testing a CMOS transistor with an electrical testing unit, the CMOS transistor being formed in a semiconductor substrate of a semiconductor wafer. A plurality of CMOS transistors are formed on the semiconductor wafer and the electrical testing unit has a support plate and a metal layer formed on the support plate. The CMOS transistor having a first terminal contact, a second terminal contact and a third terminal contact, the second terminal contact configured as an electrically open control contact and in a process step the metal layer is positioned above the semiconductor wafer over the control contact and a potential difference between the first terminal contact and a third terminal contact is generated. The control contact is capacitively coupled by applying a drive potential to the metal layer, and the function of the CMOS transistor is tested by measuring an electrical variable dependent on the capacitive coupling.