Capacitive Coupling Via for High-Frequency Chip Stacking
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Solution Overview
Problem
Current methods for forming electrical connections through electronic chips are challenging due to difficulties in precision and repeatability, especially when vias are deep, narrow, or close together, and are unsuitable for active semiconductor devices, leading to issues with signal cross-talk, capacitance, and resistance, particularly at high frequencies.
Innovation Solution
A process involving creating a via through a semiconductor chip with a doped substrate, introducing an electrically conductive material while isolating it with an insulating material, and connecting it to a signal source to propagate signals capacitively without direct electrical contact, allowing for precise control of capacitance and resistance, and enabling stacking of chips with tight spacing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional via processes are used to create through-chip electrical connections, then direct electrical contact is achieved, but manufacturing precision and repeatability deteriorate when vias are deep, narrow, or close together
Solution Approach 1:
The patent introduces an intermediary capacitive coupling mechanism between the via conductor and the chip substrate. Instead of direct electrical contact, the via conductor is positioned in close proximity to the substrate without touching it, creating a capacitive interface. This intermediary approach allows signal transmission while avoiding the manufacturing precision issues of direct contact, as the capacitive coupling is less sensitive to exact positioning and contact quality.
Solution Approach 2:
The patent replaces the mechanical direct-contact electrical connection system with an electromagnetic field-based capacitive coupling system. By substituting the mechanical contact requirement with an electric field interaction between the via conductor and substrate, the system achieves reliable signal transmission without the need for precise mechanical alignment or contact, thereby improving manufacturing precision and repeatability.
2Adaptability or versatility
If conventional processes are used on active semiconductor devices, then chip functionality is maintained, but chip damage occurs and yield is reduced
Solution Approach 1:
The patent performs the via formation and capacitive coupling structure creation as a preliminary action before final chip assembly and testing. By establishing the capacitive interfaces early in the manufacturing process, the chip can be processed and handled with greater care, reducing the risk of damage to active devices. The non-contact nature of capacitive coupling also means that subsequent handling and assembly processes are less likely to cause electrical shorts or damage to sensitive active components.
3Reliability
If large, non-scaleable packaging is used for chip-to-chip connections, then connection reliability is improved, but packaging size and cost increase
Solution Approach 1:
The patent transitions the connection architecture from a planar, two-dimensional packaging layout to a three-dimensional stacked configuration. By using capacitive coupling to enable vertical chip stacking with tight spacing, the system achieves high connection reliability through reduced signal paths and improved electrical performance, while dramatically reducing the overall packaging footprint. This dimensional change allows multiple chips to be stacked vertically rather than spread out horizontally, reducing packaging area and enabling scaleability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables reliable, high-repeatability chip-to-chip connections with controlled capacitance and resistance, suitable for high-frequency signals, and allows for the use of active semiconductor devices, reducing the need for wirebonds and minimizing chip damage during stacking.
Implementation Method 1
the electrically conductive material and the device pad being physically separated from each other but sufficiently proximate to each other so as to permit a signal that is applied to the electrically conductive material from beyond the outer side of the substrate to capacitively propagate to the device pad
Data Source
AI summary
A method of creating a semiconductor chip having a substrate, a doped semiconductor material abutting the substrate and a device pad at an outer side of the doped semiconductor material involves creating a via through at least a portion of the substrate, the via having a periphery and a bottom at a location and depth sufficient to bring the via into proximity with the device pad but be physically spaced apart from the device pad, introducing an electrically conductive material into the via, and connecting the electrically conductive material to a signal source so the signal will deliberately be propagated from the electrically conductive material to the device pad without any direct electrical connection existing between the electrically conductive material and the device pad.