Capacitive Chip Crack Detection via Stacked Rings
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Solution Overview
Problem
Current chip crack detection structures have low sensitivity, short lifetime, complex circuits, and large footprints, making them inefficient for monitoring dielectric layer cracks in chips.
Innovation Solution
A chip crack detection structure comprising multiple conductive layers in first and second chip crack detection rings and a seal ring, where the bottom surfaces of the lowermost conductive layers are not in contact with plugs, allowing for capacitance measurement between the rings to detect dielectric layer cracks, thereby enhancing sensitivity and lifetime while reducing circuit complexity and footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If resistance measurement is used to monitor dielectric layer cracks, then the detection function is achieved, but sensitivity is low
Solution Approach 1:
The patent replaces the traditional resistance measurement method with capacitance measurement. The conductive layers form a capacitor structure with the dielectric layer, where capacitance changes indicate cracks. This substitution of measurement principle (from resistance to capacitance) significantly improves detection sensitivity while maintaining reliability.
Solution Approach 2:
The patent introduces a multi-layer conductive structure stacked vertically over the dielectric layer, creating a three-dimensional capacitor. This dimensional arrangement increases the effective detection area and enhances capacitance sensitivity to cracks, overcoming the limitations of planar resistance measurement.
2Reliability
If traditional chip crack detection structure is used, then crack monitoring is achieved, but lifetime is short
Solution Approach 1:
The patent extracts the detection function from the substrate by creating suspended conductive layers that do not contact the substrate. This separation isolates the detection structure from substrate stress and degradation, extending its operational lifetime while maintaining crack monitoring capability.
Solution Approach 2:
The patent designs the conductive layers to be suspended without substrate contact, providing a buffer against mechanical stress and thermal expansion. This pre-cushioning design protects the detection structure from damage during chip operation, extending its service life.
3Measurement precision
If traditional chip crack detection structure is used, then crack detection is achieved, but circuit complexity is high
Solution Approach 1:
The patent merges multiple detection functions into a single capacitor structure. The stacked conductive layers form one integrated capacitance sensor that can detect cracks throughout the dielectric layer, eliminating the need for multiple separate resistance measurement circuits and reducing overall circuit complexity.
Solution Approach 2:
The capacitor structure serves multiple functions: it acts as both the detection element and the signal source. The same conductive layers that form the capacitor also provide the measurement signal, eliminating the need for separate excitation and sensing circuits.
4Reliability
If traditional chip crack detection structure is used, then crack monitoring is achieved, but footprint is large
Solution Approach 1:
The patent transitions from a planar detection structure to a three-dimensional stacked configuration. By stacking conductive layers vertically, the effective detection area is increased without expanding the horizontal footprint, allowing high sensitivity in a compact area.
Solution Approach 2:
The patent nests multiple conductive layers within a vertical stack, with each layer contributing to the capacitance measurement. This nested arrangement maximizes the detection capability within a minimal horizontal space, reducing the overall footprint while maintaining reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed structure increases sensitivity and lifetime while simplifying the circuit and reducing the footprint of chip crack detection, enabling effective monitoring of dielectric layer cracks through capacitance measurement between the rings.
Implementation Method 1
measuring capacitance between the first chip crack detection ring and the second chip crack detection ring
Data Source
AI summary
A chip crack detection structure, including a substrate, a first chip crack detection ring, a second chip crack detection ring, and a seal ring, is provided. The first chip crack detection ring includes multiple first conductive layers stacked over the substrate and electrically connected to each other. A bottom surface of a lowermost conductive layer among the first conductive layers is not in contact with any plug. The second chip crack detection ring surrounds the first chip crack detection ring. The second chip crack detection ring includes multiple second conductive layers stacked over the substrate and electrically connected to each other. A bottom surface of a lowermost conductive layer among the second conductive layers is not in contact with any plug. The seal ring surrounds the second chip crack detection ring. The seal ring includes multiple third conductive layers stacked over the substrate and electrically connected to each other.