Capacitive D/A Converter Reset Scheme for Lower LCD Power
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Solution Overview
Problem
Conventional D/A converters for active matrix liquid crystal display devices have high power consumption due to the need to charge and discharge capacitors corresponding to digital signal values, leading to inefficient energy use.
Innovation Solution
A D/A converter design featuring capacitors with weighted capacitances connected to a common node, a selection circuit for applying reference potentials, and a reset circuit to reduce charge transfer by using capacitive coupling for D/A conversion, thereby minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If capacitors are charged and discharged to reference voltage corresponding to digital signal values, then D/A conversion can be performed, but power consumption increases
Solution Approach 1:
The invention applies the first reference electric potential to both terminals of each capacitor in advance through the reset circuit before D/A conversion. This preliminary action initializes the capacitors to a known state, eliminating the need for repeated charging/discharging cycles and reducing power consumption while maintaining conversion accuracy
Solution Approach 2:
The invention extracts the power-consuming charging/discharging operation from the D/A conversion process. By separating the initialization function (performed once by the reset circuit) from the conversion function (performed by the selection circuit), the patent eliminates redundant energy consumption while preserving the essential D/A conversion capability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution reduces power consumption by approximately 50% by limiting charge transfer to capacitive coupling during D/A conversion, enhancing energy efficiency in digital-to-analog signal conversion.
Implementation Method 1
a plurality of capacitors, capacitance of each of which is weighted according to a weight of each bit of digital signals
Implementation Method 2
a reset circuit that applies the first reference electric potential to both terminals of each of the capacitors in response to a reset signal
Implementation Method 3
an amount of electric charges that is charged and discharged as the D/A conversion is performed is reduced to reduce the power consumption, since the D/A conversion is performed only by transferring electric charges through capacitive coupling
Data Source
AI summary
A D/A converter with reduced power consumption is offered by reducing an amount of electric charges that is charged and discharged as D/A conversion is performed. A terminal of each of four capacitors C1, C2, C3 and C4 is connected to a common node. The capacitors C1, C2, C3 and C4 have capacitances C, C, 2C and 4C, respectively. A selection circuit SEL is provided with selection transistors ST1, ST2, ST3, ST4, ST5 and ST6, and selects and outputs either a first reference electric potential V1 or a second electric potential V2 according to a value of each bit of the digital signals D0, D1 and D2. Each of transfer transistors TT1, TT2 and TT3 transfers each of outputs of the selection circuit SEL to another terminal of corresponding each of the capacitors C2, C3 and C4, respectively, in response to a start pulse STP. Each of reset transistors RT1, RT2, RT3 and RT4 connects the terminal with the other terminal of corresponding each of the capacitors C1, C2, C3 and C4, and applies the first reference electric potential V1 to both the terminal and the other terminal in response to a reset pulse RST.