Capacitive DAC DTC Circuit for Constant-Slope Delay Linearity
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Solution Overview
Problem
Constant slope digital-to-time converters (DTCs) face challenges in achieving high linearity due to variable delay element slopes, which can be exacerbated by the need for separate charging capacitors, increasing complexity and noise in low-noise applications like 5G communication systems.
Innovation Solution
A digital-to-time converter (DTC) circuit that incorporates a capacitive digital-to-analog converter (CDAC) functioning as both a DAC and a charging capacitor, generating input control word dependent voltages to produce a constant slope ramp voltage, reducing the DTC's profile and complexity by eliminating the need for a separate charging capacitor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a separate charging capacitor is used in constant slope DTC, then the DTC can generate a voltage ramp, but the device complexity and noise increase
Solution Approach 1:
The patent combines the DAC and charging capacitor into a single integrated structure. The capacitive DAC serves dual functionality: it generates the input control word dependent voltage and simultaneously acts as the charging capacitor for the delay element. This merging eliminates the need for a separate charging capacitor, reducing device complexity while maintaining the constant slope characteristic and linearity performance.
Solution Approach 2:
The capacitive DAC is designed to perform multiple functions: it operates as a digital-to-analog converter to generate control voltages and simultaneously functions as the charging capacitor that provides the ramp voltage to the delay element. This multi-functionality reduces the overall component count and circuit complexity while preserving the required performance characteristics.
2Reliability
If variable slope DTC is used, then the DTC can produce delay by varying slope, but linearity deteriorates due to different detector delays
Solution Approach 1:
The patent maintains a constant slope of the voltage ramp by carefully controlling the charging current and capacitor parameters. The input control word affects only the starting voltage of the ramp, not its slope. This parameter control ensures that the delay element operates consistently across different delay settings, improving linearity by eliminating variations in detector delays that would occur with variable slope approaches.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves linearity and reduces non-linear sources of noise, enhancing the performance of DTCs in applications requiring high linearity, such as fractional-N phase-locked loop designs for 5G communication systems.
Implementation Method 1
a first switch connected between a first power source and a second node, and configured to provide a charge current to the second node
Implementation Method 2
the DAC circuit is configured to generate an input control word dependent voltage according to an input control word
Implementation Method 3
generating a ramp voltage having a constant or substantially constant slope
Data Source
AI summary
A DTC circuit, includes: a DAC connected to a first node; a first switch connected between a first power source and a second node, and to provide a charge current to the second node according to a first switching signal; and a second switch connected between the first node and the second node, and to electrically connect the DAC to the second node according to a second switching signal. The DAC is to be charged to generate a voltage ramp corresponding to the charge current during a first DTC operational phase when the first and second switching signals have an active level to turn on the first and second switches, and to generate an input control word dependent voltage according to an input control word during a second DTC operational phase when the first and second switching signals have an inactive level to turn off the first and second switches.