Multi-Level Capacitive DAC Sequencing for High-Linearity Sigma-Delta Feedback
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Solution Overview
Problem
Conventional sigma delta analog-to-digital converters require high-linearity digital-to-analog converters in feedback loops, which are challenging to achieve with multi-level charge transfer DACs, especially when using minimal capacitors and dynamic element matching, as inaccuracies in the DAC directly affect the signal and are difficult to compensate for.
Innovation Solution
A multi-level charge transfer DAC with a minimal number of capacitors and capacitive switches, utilizing a sequencer to control switching sequences that generate multiple output levels by transferring charges proportionally to the sum of capacitors, with alternative sequences for non-proportional levels and pseudo-random sequence shuffling to maintain linearity and reduce noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional charge transfer DACs are used with minimal capacitors, then device complexity is reduced, but manufacturing precision deteriorates due to difficulty in achieving high linearity
Solution Approach 1:
The DAC is divided into multiple sub-DACs, each handling a portion of the total output levels. This segmentation allows each sub-DAC to use fewer capacitors while maintaining overall high linearity through the combined output of multiple segmented units, resolving the contradiction between minimal capacitors and high precision.
Solution Approach 2:
The patent implements dynamic element matching (DEM) techniques where capacitor assignments are dynamically switched based on input codes rather than being statically fixed. This dynamic reconfiguration compensates for capacitor mismatch errors, enabling high linearity precision even with minimal capacitors, thus resolving the contradiction between device complexity and manufacturing precision.
2Measurement precision
If multi-level DACs are implemented to reduce quantization noise, then measurement precision is improved, but device complexity increases due to multiple capacitors and matching sequences
Solution Approach 1:
The multi-level DAC is segmented into multiple sub-DACs that can be independently controlled. This allows the system to achieve multi-level output capability (reducing quantization noise) without requiring a single large capacitor array, thus reducing overall device complexity while maintaining measurement precision.
Solution Approach 2:
The patent designs capacitor structures that serve multiple functions: they participate in different charge transfer sequences for different output levels, and can be dynamically reassigned through DEM. This multi-functionality allows fewer capacitors to achieve multi-level precision output, resolving the contradiction between measurement precision and device complexity.
3Manufacturing precision
If dynamic element matching sequences are used to maintain linearity, then manufacturing precision is improved, but device complexity increases due to switching sequences
Solution Approach 1:
The complex DEM switching sequences are divided and distributed across multiple sub-DACs. Each sub-DAC implements simpler local switching sequences, and the overall linearity is maintained through the coordinated operation of segmented units, reducing the complexity burden on any single switching sequence while preserving manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of sigma delta converters with more levels than conventional systems using the same size and power, achieving higher accuracy and stability with reduced quantization noise and improved distortion behavior.
Implementation Method 1
A multi-level capacitive digital to analog converter (DAC) of the charge transfer type for use in a sigma delta modulator for generating N output levels, wherein an output level is defined by a respective amount of charge transferred by the DAC
Data Source
AI summary
A digital-to analog converter (DAC) of the charge transfer type can be used in a sigma delta modulator for generating N output levels, wherein an output level is defined by a respective amount of charge transferred by the DAC. The DAC has a first capacitor switch unit receiving a reference voltage and a first digital input value to transfer first output charges, at least one second capacitor switch unit receiving the reference voltage and a second digital input value, wherein an output of the second capacitor switch unit is coupled in parallel with an output of the first capacitor switch unit to generate a sum of first and second transferred output charges; and a sequencer controlling switches of the first and second capacitor switch units wherein switching sequences according to individual first and second digital input values are provided for every DAC input value to generate the N output levels.