Capacitive DAC Switching Scheme for Low-INL Linearity
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Solution Overview
Problem
Conventional digital-to-analog converters suffer from degradation in linearity due to transient behavior, leading to non-linear operation and significant Integral Non-Linearity (INL) errors, especially when high linearity is required.
Innovation Solution
The proposed solution involves a modified circuit layout and clocking scheme where the second capacitor (C2) is charged to a voltage proportional to the voltage across the first capacitor (CI) before switching, and then connected in parallel, reducing charge sharing and voltage spikes, thereby maintaining linear relationships between voltages and minimizing INL errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional digital-to-analog converter circuit is used, then device complexity is low, but manufacturing precision (linearity) deteriorates due to transient behavior and voltage spikes
Solution Approach 1:
The patent charges the second capacitor C2 to a voltage proportional to the voltage across the first capacitor CI before switching them into parallel connection. This preliminary charging action ensures that when the capacitors are connected in parallel, there is minimal voltage difference between them, thereby reducing voltage spikes and maintaining linear operation during the charging phase.
Solution Approach 2:
The patent introduces an intermediate charging mechanism where the second capacitor C2 is charged through a charging path from the digital-to-analog converter array output before being connected in parallel with the first capacitor CI. This intermediary charging step acts as a buffer that prevents direct voltage conflict and reduces transient effects during the switching operation.
2Measurement precision
If conventional switching scheme is used, then device complexity is low, but measurement precision (INL performance) deteriorates due to voltage drops and spikes
Solution Approach 1:
The patent implements a modified clocking scheme that includes a preliminary charging phase for the second capacitor C2 before the main switching operation. The clocking signals are designed to first charge C2 to the appropriate voltage level, then subsequently connect it in parallel with CI. This preliminary action eliminates voltage spikes during switching and significantly improves INL performance.
Solution Approach 2:
The patent uses periodic clocking signals to control the switching of capacitors in a systematic sequence. The clocking scheme periodically charges and discharges the capacitors in controlled phases, ensuring that the second capacitor is always properly charged before being switched into parallel connection, thereby maintaining consistent linear operation throughout the conversion process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly improves INL performance by reducing voltage drops and spikes, achieving INL values of +/â0.0065 LSB (typical) and +/â0.12 LSB (worst case), representing an improvement of about two orders of magnitude and one order of magnitude respectively over conventional methods.
Implementation Method 1
a second capacitor C2 adapted to be selectively coupled in parallel with the first capacitor CI to share charge therewith
Implementation Method 2
the second capacitor C2 adapted to be selectively coupled in parallel with the first capacitor CI to share charge therewith
Data Source
AI summary
In some embodiments, a circuit for use in devices involving digital-to-analog conversion of signals includes: a capacitive digital-to-analog converter array and an amplifier. The capacitive digital-to-analog converter includes an input port for receiving a digital input signal and an output port. The amplifier includes capacitive feedback loops that include a first capacitor coupling the output of the amplifier with the input of the amplifier and a second capacitor coupled to the output port of the digital-to-analog converter array at the input of the amplifier. The circuit further includes a set of switches that include a first switch and a second switch coupled with opposed ends of the second capacitor at the input and at the output of the amplifier, respectively.