Capacitive DAC Switching for 4N+1 Levels With Mismatch Linearity
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Solution Overview
Problem
Sigma delta modulators require high-linearity digital-to-analog converters (DACs) for accurate analog-to-digital conversion, but multi-level DACs with more than five levels are complex and sensitive to capacitor mismatch, affecting signal transfer and linearity.
Innovation Solution
A charge transfer type DAC with a capacitor switch unit generating 4n+1 output levels, using a plurality of reference capacitor pairs and a switching controller to achieve linearity through specific switching configurations for even and odd transfers, minimizing the need for dynamic element matching and maintaining linearity despite capacitor mismatch.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multi-level DAC with more than five levels is implemented using multiple capacitors, then the output resolution is improved, but the device complexity increases and sensitivity to capacitor mismatch worsens
Solution Approach 1:
The patent divides the multi-level DAC into multiple 5-level sub-DACs, where each sub-DAC handles a portion of the output levels. This segmentation allows the system to achieve high resolution (4n+1 levels) while keeping each individual capacitor array manageable and less sensitive to mismatch, as each sub-DAC only requires 5 levels rather than the full multi-level range.
2Measurement precision
If multi-level DAC with more than five levels is implemented using multiple capacitors, then the output resolution is improved, but the sensitivity to capacitor mismatch worsens
Solution Approach 1:
By segmenting the multi-level DAC into multiple 5-level sub-DACs, the patent reduces the capacitor mismatch sensitivity in each sub-DAC. Each sub-DAC only needs to accurately generate 5 levels, which is less sensitive to capacitor variations than generating many more levels in a single DAC, thereby improving overall reliability.
Solution Approach 2:
The patent combines multiple 5-level sub-DACs to form the complete multi-level DAC. By merging the outputs of these sub-DACs with reduced individual mismatch sensitivity, the system achieves high output resolution while maintaining reliability, as the errors from individual sub-DACs can be averaged or canceled through the combining process.
3Manufacturing precision
If dynamic element matching is used to achieve linearity in multi-level DAC, then the linearity is improved, but the device complexity and power consumption increase
Solution Approach 1:
The patent segments the multi-level DAC into multiple 5-level sub-DACs, each requiring simpler switching configurations. This segmentation reduces the complexity of implementing dynamic element matching, as each sub-DAC has fewer elements to match and switch, thereby maintaining linearity with reduced overall device complexity.
4Manufacturing precision
If dynamic element matching is used to achieve linearity in multi-level DAC, then the linearity is improved, but the power consumption increases
Solution Approach 1:
By dividing the multi-level DAC into multiple 5-level sub-DACs, the patent reduces the power consumption required for dynamic element matching. Each sub-DAC requires less switching activity and fewer matched elements, leading to lower individual power consumption that sums to less than a monolithic multi-level DAC would require for equivalent linearity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables more accurate and stable sigma delta devices with reduced complexity and power consumption, maintaining linearity across multiple capacitor configurations, thus improving the performance of sigma delta modulators.
Implementation Method 1
capacitive charge transfer DACs are often used to realize the feedback of the modulator
Implementation Method 2
each output level is defined by a different amount of electrical charge transferred to the output of the DAC
Data Source
AI summary
A digital-to analog converter (DAC) of the charge transfer type for use in a sigma delta modulator, includes a capacitor switch unit operable to generate a 4n+1 output levels, comprising: a plurality of second switching units for coupling first terminals of a plurality of reference capacitor pairs with either a positive or a negative reference signal; wherein the second terminals of the plurality of reference capacitor pairs are coupled in parallel, respectively; wherein for even transfers a single switching combination is provided to achieve linearity and wherein for odd transfers an average of different switching combinations is provided to achieve linearity; wherein an even transfer is when an input of the DAC is even and an odd transfer is when an input to the DAC is odd.