Capacitive DAC Pre-Charge Scheme for Stable Reference Loading
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Solution Overview
Problem
Conventional digital-to-time converters experience nonlinear delay generation and voltage droop due to significant changes in loading on the voltage reference circuit, especially when handling near-integer divide values, leading to performance issues in capacitive digital-to-analog conversion.
Innovation Solution
The method involves partitioning the conversion period into pre-charge, selective discharge, and shift intervals to maintain a constant average load on the voltage reference, reducing data-dependent loading by pre-charging and selectively discharging capacitors based on input digital signals, thereby stabilizing the output voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional capacitive digital-to-analog converter selectively pre-charges switched-capacitor nodes according to input digital code, then output voltage accuracy is improved, but data-dependent loading on voltage reference circuit increases causing voltage droop and nonlinear delay
Solution Approach 1:
The patent applies preliminary action by pre-charging all switched-capacitor nodes to the reference voltage in a first interval before the selective discharge phase. This ensures that regardless of the input digital code, all nodes start from the same charged state, eliminating data-dependent variations in the loading pattern on the voltage reference circuit and preventing voltage droop.
Solution Approach 2:
The patent implements periodic action by structuring the conversion cycle into distinct time intervals: a first interval for uniform pre-charging all capacitive elements, a second interval for selective discharge based on input data, and a third interval for holding the output. This periodic structure ensures that every conversion cycle draws the same total charge from the voltage reference, making the loading independent of the input digital code.
2Manufacturing precision
If capacitive digital-to-analog converter handles near-integer divide values, then timing resolution is improved, but loading on voltage reference circuit changes significantly causing nonlinear delay generation
Solution Approach 1:
By pre-charging all switched-capacitor nodes to the reference voltage before the selective discharge phase, the patent ensures that the voltage reference circuit experiences consistent loading conditions regardless of the input digital code value. This preliminary charging action eliminates the significant loading changes that occur when handling near-integer divide values, maintaining linear delay generation across the full input range.
3Measurement precision
If conventional converter draws variable charge from voltage reference based on input code, then output voltage corresponds to input digital code, but jitter performance deteriorates due to data-dependent loading
Solution Approach 1:
The patent structures the conversion process into periodic intervals where the total charge drawn from the voltage reference circuit is constant for every input digital code. The first interval uniformly charges all nodes, and the second interval selectively discharges them based on input data, but the sum of charge transactions remains constant. This periodic structure with constant total loading eliminates data-dependent variations that cause jitter, while still maintaining accurate output voltage correspondence to the input code.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves jitter performance and near-integer divide values by maintaining a consistent charge delivery from the voltage reference, reducing data-dependent loading and enabling higher frequency operation in timing circuits.
Implementation Method 1
capacitive digital-to-analog converter includes a capacitor having a first terminal and a second terminal
Data Source
AI summary
A method for reducing data-dependent loading on a voltage reference pre-charges a capacitor of the capacitive digital-to-analog converter to configure the capacitor in a pre-charged state during a first interval. The method selectively discharges the capacitor from the pre-charged state according to a value of an input digital signal to configure the capacitor in a selectively discharged state during a second interval. The method holds an output node of the capacitive digital-to-analog converter at a reset voltage level during the first interval and the second interval. The output node is coupled to a first terminal of the capacitor. The method discharges any remaining charge on the capacitor and providing an output voltage signal to an output node of the capacitive digital-to-analog converter according to the selectively discharged state during a third interval. The output voltage signal has a voltage level corresponding to a value of the input digital signal.