Capacitive DAC Cell With Series Resistor for RF Linearity
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Solution Overview
Problem
Current Digital-to-Analog Converters (DACs), particularly those in Metal-Oxide-Semiconductor technology, face challenges in linearity due to non-linear MOS resistance, leading to harmonic distortion and degraded Error Vector Magnitude (EVM) in RF signals, which affects Adjacent Channel Leakage Ratio (ACLR).
Innovation Solution
Incorporating a resistive element with a resistance of at least 50Ω between the inverter circuit and capacitive element in DAC cells, and using transistors with low threshold voltage to linearize the output stage, reducing parasitic capacitance and achieving a nearly perfect rectangular waveform.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If MOS transistors are used in DAC cells, then the DAC can be manufactured with standard semiconductor processes, but the non-linear MOS resistance causes harmonic distortion and degrades linearity
Solution Approach 1:
A resistive element is introduced as an intermediary component between the inverter output and the capacitive element. This resistor linearizes the overall transfer function by compensating for the non-linear MOS resistance, thereby improving linearity while maintaining manufacturability with standard semiconductor processes
Solution Approach 2:
The resistance value of the added resistive element is specifically designed to compensate for the non-linear characteristics of the MOS transistors. By adjusting this parameter, the overall transfer function becomes more linear, reducing harmonic distortion without requiring changes to the manufacturing process
2Ease of manufacture
If the on-resistance of NMOS and PMOS components are not exactly equal, then the DAC can be implemented with standard MOS technology, but this causes harmonic distortion and degrades ACLR
Solution Approach 1:
The resistive element serves as a mediator that equalizes the effective resistance seen by the capacitive element, compensating for the mismatch between NMOS and PMOS on-resistances. This reduces harmonic distortion and improves ACLR while maintaining the benefits of standard MOS technology implementation
3Manufacturing precision
If a resistive element with at least 50Ω resistance is added between the inverter circuit and capacitive element, then DAC linearity is significantly improved, but device complexity increases
Solution Approach 1:
The DAC cell is segmented into distinct functional blocks: the inverter circuit, the resistive element, and the capacitive element. This segmentation allows each component to be optimized independently and simplifies the overall design and analysis, making the added complexity manageable and beneficial
4Manufacturing precision
If transistors with low threshold voltage are used to linearize the output stage, then linearity improves, but power consumption may increase
Solution Approach 1:
Transistors with low threshold voltage are used in the inverter circuit to improve linearity. The low threshold voltage allows for better control of the switching behavior and reduces the non-linear effects, achieving improved linearity while managing power consumption through optimized device sizing and biasing
Data Source
AI summary
A digital-to-analog converter is provided. The digital-to-analog converter includes a plurality of digital-to-analog converter cells coupled to an output node of the digital-to-analog converter. At least one of the plurality of digital-to-analog converter cells includes a capacitive element configured to provide an analog output signal of the digital-to-analog converter cell to the output node. Further, the at least one of the plurality of digital-to-analog converter cells includes an inverter circuit coupled to the capacitive element. The inverter circuit is configured to generate an inverter signal for the capacitive element based on an oscillation signal. The at least one of the plurality of digital-to-analog converter cells additionally includes a resistive element coupled to the inverter circuit and the capacitive element. A resistance of the resistive element is at least 50Ω.