Capacitive Multi-Level DAC Switching for Linear Sigma-Delta Modulators
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Solution Overview
Problem
Multi-bit sigma-delta modulators face challenges in realizing a linear multi-bit digital-to-analog converter due to non-linearity, leading to harmonic distortions and increased noise floor, which is exacerbated by the need for dynamic element matching that increases digital complexity and circuit area, making them unsuitable for area-limited applications like pixel ADCs in imaging.
Innovation Solution
A multi-level capacitive digital-to-analog converter is designed using simple circuits with a small area, employing a capacitor switch circuit with differential operational amplifiers and controllable switches, allowing for a large dynamic range without the need for dynamic element matching, by generating multiple output levels through controlled switching signals in two operational phases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If dynamic element matching is used to reduce DAC non-linearity sensitivity, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent extracts the non-linearity correction function from the digital domain to the analog domain by using a dedicated calibration circuit that physically measures and compensates for capacitor mismatches. This removes the need for complex digital element matching algorithms, reducing digital complexity while maintaining measurement precision.
Solution Approach 2:
The patent introduces an intermediary calibration circuit that acts as a mediator between the physical capacitors and the digital control logic. This calibration circuit measures actual capacitor values and provides corrected control signals, serving as an intermediary that simplifies the overall system complexity while improving DAC linearity.
2Measurement precision
If dynamic element matching is used to reduce DAC non-linearity sensitivity, then measurement precision is improved, but area of stationary object increases
Solution Approach 1:
The patent merges the calibration function with the existing DAC structure by using the same capacitor array and switching infrastructure. The calibration circuit reuses existing components rather than adding separate correction hardware, thereby improving measurement precision without significantly increasing circuit area.
Solution Approach 2:
The patent makes the capacitor array and switching network multi-functional by using them for both normal DAC operation and calibration measurements. This universal usage allows the system to achieve high measurement precision without dedicating separate hardware resources, thus avoiding area increase.
3Productivity
If a multi-bit sigma-delta modulator uses a capacitive DAC, then productivity is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent implements a feedback-based calibration mechanism where the actual capacitor values are measured and used to adjust control signals. This feedback loop compensates for manufacturing variations in capacitor values, allowing high productivity through multi-bit operation without requiring extremely tight manufacturing precision.
Solution Approach 2:
The patent changes the operating parameters of the DAC by dynamically adjusting control signals based on measured capacitor values. This parameter adjustment compensates for manufacturing variations, enabling high-resolution operation without demanding stringent capacitor matching tolerances during manufacturing.
Data Source
AI summary
A multi-level capacitive digital-to-analog converter, comprises at least one capacitor switch circuit (100) including a differential operational amplifier (130) having a first input node (E130a) and a second input node (E130b). A first current path (101) is coupled to a first reference input terminal (E100a) to apply a first reference potential (RefP) and the second current path (102) is coupled to a second reference input terminal (E100b) to apply a second reference potential (RefN). The at least one capacitor switch circuit (100) comprises a first controllable switch (111) being arranged between the second input node (E130a) of the differential operational amplifier (130) and the first current path (101). The at least one capacitor switch circuit (100) comprises a second controllable switch (112) being arranged between the first input node (E130a) of the differential operational amplifier (130) and the second current path (102).