Capacitive DAC Structure With Switch-Timed Vcm Generation
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Solution Overview
Problem
The traditional SAR ADC architecture faces challenges in high power consumption and large area due to the Vcm voltage generation circuit, especially in high-speed applications, which limits its performance and scalability.
Innovation Solution
A novel capacitive DAC structure is introduced, incorporating a fully differential DAC capacitor array, a comparator, and a sampling and holding switch, utilizing logic switches and timing control to generate the common mode level Vcm without additional capacitors or operational amplifiers, reducing power consumption and area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a traditional Vcm voltage generation circuit (voltage divider or current mirror bias) is used, then the common mode voltage is stable, but the power consumption and area increase linearly with speed
Solution Approach 1:
The patent extracts the Vcm voltage generation function from the traditional dedicated voltage divider or current mirror circuit and relocates it to the DAC capacitor array. By reusing the existing DAC capacitors and their charge redistribution mechanism, the separate Vcm generation circuit is eliminated, thereby reducing power consumption and area while maintaining Vcm stability through the same charge conservation principle
Solution Approach 2:
The DAC capacitor array is given multiple functions: it serves both as the digital-to-analog conversion element and as the Vcm voltage generation mechanism. The same capacitors that perform DAC functionality also generate the common mode voltage through charge redistribution, eliminating the need for dedicated Vcm generation components and reducing overall circuit complexity
2Reliability
If a traditional Vcm voltage generation circuit is used, then the common mode voltage is stable, but the circuit area increases
Solution Approach 1:
The patent merges the Vcm generation function with the DAC capacitor array structure. The upper electrode plates of the DAC capacitors serve dual purposes: storing signal charges for DAC operation and generating the common mode voltage. This consolidation eliminates separate Vcm generation circuitry and reduces the overall circuit area
Solution Approach 2:
The DAC capacitor array performs multiple functions simultaneously: analog-to-digital conversion and common mode voltage generation. By making the DAC capacitors multi-functional, the patent eliminates the need for additional dedicated Vcm generation components, thereby reducing circuit area
3Productivity
If the sampling stage proportion increases for high-speed applications, then the sampling rate improves, but the power consumption of Vcm generation increases
Solution Approach 1:
The patent employs periodic charge redistribution cycles in the DAC capacitor array to generate Vcm dynamically during the sampling stage. Instead of continuous static power consumption from traditional bias circuits, the system uses periodic switching and charge redistribution that aligns with the high-speed sampling requirements, reducing average power consumption while maintaining high sampling rates
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The new structure effectively reduces power consumption and area, enhancing the IP competitiveness and enabling high-performance ADC design by stabilizing Vcm through charge redistribution and logic switch design.
Implementation Method 1
a capacitive DAC structure is provided, which at least comprises a fully differential DAC capacitor array
Implementation Method 2
utilizing logic switches and timing control to generate the common mode level Vcm without additional capacitors or operational amplifiers
Data Source
AI summary
This application provides a novel capacitive DAC structure, which at least includes a fully differential DAC capacitor array, a comparator, and a sampling and holding switch provided between the fully differential DAC capacitor array and the comparator. In this application, by providing the sampling and holding switch, including a first logic switch, a second logic switch and a third logic switch, between the fully differential DAC capacitor array and the comparator, and changing the timing relationship of the switches to generate a stable common mode level Vcm, the area and power consumption can be greatly reduced, the IP competitiveness can be effectively improved, and it can be used for high-performance ADC design.