Capacitive DFE Feedback Circuit for Faster ISI Compensation
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Solution Overview
Problem
In high-speed communication applications, Decision Feedback Equalization (DFE) systems face challenges in settling feedback signals within a timely manner due to intersymbol interference (ISI), leading to errors and reduced orthogonality of correction, especially as data rates increase, causing issues with closed-loop timing and increased power requirements.
Innovation Solution
The implementation of a capacitive coupling feedback circuit in the tap feedback path of DFE systems, which generates a capacitive weighted signal based on the capacitance of a subset of capacitors, improves closed-loop timing by eliminating the need for a summation circuit and reduces power consumption by minimizing loading on wideband amplifiers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If traditional DFE feedback circuits are used, then feedback signals can be generated, but the settling time is excessive and closed-loop timing is compromised
Solution Approach 1:
The patent extracts and eliminates the summation circuit from the traditional DFE feedback path. By removing this component, the feedback signal is directly coupled to the data input signal without requiring summation operations, thereby reducing settling time and improving closed-loop timing while maintaining the essential feedback functionality.
Solution Approach 2:
The patent introduces an intermediary capacitive coupling mechanism that directly transfers the feedback signal to the data input signal. This capacitive coupling acts as a mediator that eliminates the need for traditional summation circuits and wideband amplifiers, reducing settling time while preserving signal integrity and closed-loop timing.
2Use of energy by moving object
If traditional DFE circuits with summation circuits are used, then feedback can be applied, but power consumption is excessive due to loading on wideband amplifiers
Solution Approach 1:
The patent removes the wideband amplifier and summation circuit from the feedback path, eliminating the excessive loading and associated power consumption. The capacitive coupling directly interfaces the feedback signal with the data input signal, maintaining feedback accuracy while dramatically reducing power requirements.
Solution Approach 2:
The patent replaces the traditional electromechanical summation circuit and wideband amplifier with a capacitive coupling mechanism. This substitution eliminates the need for high-power amplification and summation operations, reducing power consumption while preserving the feedback functionality through direct capacitive signal transfer.
3Productivity
If data rate is increased to improve productivity, then communication speed improves, but ISI effects increase causing more errors
Solution Approach 1:
The patent implements a direct feedback mechanism through capacitive coupling that feeds back the detected data input signal to compensate for ISI effects. This feedback loop operates effectively at high data rates by directly counteracting intersymbol interference without the delays and errors associated with traditional summation circuits, thereby maintaining reliability at high productivity levels.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the accuracy of bit detection by reducing DFE errors, improving orthogonality of correction, and reducing power requirements, thereby improving the eye-opening of the communication system's eye diagram.
Implementation Method 1
a capacitive coupling feedback circuit that can include a plurality of capacitors and can be configured to generate the capacitive weighted signal corresponding to a weighted detected bit of the previously received bit based on a capacitance of a subset of capacitors of the plurality of capacitors
Data Source
AI summary
In some examples, a receiver can include a sampler circuit that can be configured to process a data input signal corresponding to a current bit received at a receiver based on a capacitive weighted signal to compensate for distortion effects that a previously received bit at the receiver has on the data input signal. The receiver can include a capacitive coupling feedback circuit that can be configured to generate the capacitive weighted signal corresponding to a weighted detected bit of the previously received bit based on a capacitance of a subset of capacitors of a plurality of capacitors of the feedback circuit. The capacitive coupling feedback circuit can be configured to selectively control a number of capacitors of the plurality of capacitors that are connected in parallel corresponding to the subset of capacitors to control an amount of weight applied to the detected bit to generate the capacitive weighted signal.