Differential Comparator Circuit With Capacitive Dividers for Low-Voltage ADCs
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Solution Overview
Problem
Existing analog to digital converters (ADCs) face limitations in operating with low voltage supplies and have restricted signal swing capabilities, leading to noise issues and insufficient pixel swing for certain applications.
Innovation Solution
A differential comparator circuit with a capacitive voltage amplifier and capacitive dividers generates differential analog and ramp signals, allowing for comparison at a fixed common mode, enabling operation with low voltage supplies and increased signal swing without noise increase.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If existing ADCs are used with low voltage supplies (2V or less), then power consumption is reduced, but the signal swing capability is limited by the supply voltage
Solution Approach 1:
The patent transitions from single-ended signal processing to differential signal processing, adding a second dimension to the signal domain. By using differential comparators that compare voltage differences rather than absolute voltages, the circuit can handle larger signal swings while operating from low voltage supplies, as the differential voltage can exceed the supply voltage through proper biasing and signal conditioning
Solution Approach 2:
The invention changes the operating parameters by implementing a differential architecture with specific common-mode voltage biasing. The differential comparator circuit uses tailored common-mode voltage levels and differential signal conditioning to enable enhanced signal swing capability while maintaining compatibility with low voltage supply operation, effectively decoupling signal swing range from supply voltage constraints
2Adaptability or versatility
If the supply voltage is increased to increase signal swing, then signal swing capability is improved, but power consumption increases
Solution Approach 1:
The patent employs differential signaling that operates in a different voltage domain, allowing signal swings to be referenced to a common-mode voltage rather than ground. This enables the signal to swing beyond the supply voltage rails through differential voltage development, achieving large signal swings without requiring proportionally higher supply voltages and thus maintaining low power consumption
3Device complexity
If existing ADC architectures are used, then the design is simple, but noise performance is insufficient
Solution Approach 1:
The patent segments the signal processing into differential pairs throughout the comparator circuit, including differential capacitive dividers, differential amplification stages, and differential comparison. This segmentation into balanced differential paths rejects common-mode noise and interference, significantly improving noise performance while adding manageable complexity through systematic differential architecture
Solution Approach 2:
The invention converts the potential harm of circuit complexity into benefit by using differential architecture that inherently provides noise rejection and common-mode rejection. The additional circuit elements required for differential operation simultaneously provide noise filtering and signal integrity enhancement, turning the complexity burden into a noise-rejection advantage
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution allows ADCs to operate effectively with low voltage supplies and increases the signal swing capability, reducing noise and enabling broader application use while maintaining low power consumption.
Implementation Method 1
a voltage amplifier of negative gain configured to receive an analog input signal and to generate an inverted analog input signal
Implementation Method 2
a first capacitive divider configured to generate a first signal as an average of the analog input signal and a first ramp signal; a second capacitive divider configured to generate a second signal as an average of the inverted analog input signal and a second ramp signal
Data Source
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AI summary
A differential comparator circuit (300) comprising: - a voltage amplifier (325) of negative gain to receive an analog input signal (VX) and to generate an inverted analog input signal (VXP), wherein the analog input signal (VX) and the inverted analog input signal (VXP) form differential analog input signals; and - a comparator input circuit (305) comprising: a first capacitive divider (310) to generate a first signal (INN) as an average of the analog input signal (VX) and a first ramp signal (RMPP); - a second capacitive divider (320) to generate a second signal (INP) as an average of the inverted analog input signal (VXP) and a second ramp signal (RMPN), wherein the first and second ramp signals (RMPP, RMPN) are differential ramp signals; the comparator being configured to compare the first (INN) and second signals (INP) to generate a signal transition having a timing based on the input signal (VX).