Capacitive Divider Sensing for Resistance Variable Memory
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Solution Overview
Problem
Existing memory technologies face challenges in efficiently sensing and programming resistance variable memory cells, particularly in achieving low power consumption and fast power-up times while accurately determining multiple resistance states in phase change memory devices.
Innovation Solution
The implementation of a capacitive divider as part of a sensing scheme that generates multiple reference levels, allowing for efficient comparison with the output of resistance variable memory cells, thereby enabling low average power consumption and fast power-up times in sensing operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional sensing schemes are used for resistance variable memory cells, then measurement precision can be achieved, but power consumption increases and power-up time increases
Solution Approach 1:
The patent replaces conventional resistive voltage dividers with a capacitive divider circuit. The capacitive divider uses capacitors instead of resistors to generate reference voltages, eliminating continuous DC current consumption while maintaining the ability to generate multiple reference levels for accurate resistance state determination. This substitution of mechanical/electrical components (resistors) with alternative components (capacitors) resolves the contradiction between measurement precision and power consumption.
Solution Approach 2:
The capacitive divider is charged periodically to generate reference voltages only when needed for sensing operations, rather than maintaining continuous voltage levels through resistive dividers. This periodic charging approach reduces average power consumption while still providing the necessary reference levels for accurate measurement when sensing is performed.
2Measurement precision
If conventional sensing schemes are used for resistance variable memory cells, then measurement precision can be achieved, but power-up time increases
Solution Approach 1:
The capacitive divider circuit charges rapidly through low-impedance paths compared to resistive dividers, enabling fast establishment of reference voltages. The capacitive nature of the circuit allows quick voltage transitions and minimal settling time, reducing power-up time while maintaining measurement precision through accurate reference level generation.
3Measurement precision
If multiple reference levels are generated for multistate memory sensing, then measurement precision improves, but device complexity increases
Solution Approach 1:
The capacitive divider circuit serves multiple functions: it generates multiple reference voltages simultaneously, provides a stable voltage reference, and enables sensing of multiple resistance states without requiring separate circuitry for each reference level. This multi-functionality reduces overall device complexity compared to schemes requiring multiple independent voltage reference generators.
Solution Approach 2:
The capacitive divider is segmented into multiple capacitive elements (C1, C2, C3, etc.) that can be independently configured to generate different reference voltage levels. This segmentation allows flexible generation of multiple reference levels from a single circuit structure, achieving high measurement precision for multistate memory while avoiding the complexity of multiple separate voltage reference circuits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for accurate determination of resistance states in resistance variable memory cells with reduced power consumption and rapid power-up times, enhancing the efficiency of memory device operations.
Implementation Method 1
a capacitive divider, which can include a first capacitor coupled to a second capacitor in series
Data Source
AI summary
The present disclosure includes devices and methods for sensing resistance variable memory cells. One device embodiment includes at least one resistance variable memory cell, and a capacitive divider configured to generate multiple reference levels in association with the at least one resistance variable memory cell.