Capacitive Divot Depth Measurement in Semiconductor STI Regions
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Solution Overview
Problem
The formation of divots in shallow trench isolation structures can lead to current leakage paths and 'foot shorts' in semiconductor devices, causing yield plummeting, as existing methods are either destructive or ineffective in early detection and process control feedback.
Innovation Solution
A method and test structure for capacitive measurement of divots, involving the measurement of capacitance differences between regions with and without divots, allowing for non-destructive inline signal monitoring and quick process control feedback, enabling characterization of divot depth during manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If capacitive measurement method is used to detect divots, then non-destructive early detection and process control feedback are enabled, but measurement precision and reliability are challenged by the need to distinguish divot capacitance from other capacitance sources
Solution Approach 1:
The capacitance measurement is segmented into multiple components: C1 (total capacitance at first contact), C2 (capacitance of gate lines completely over active region), and C3 (capacitance of gate lines over STI region). By measuring and subtracting these segmented components, the divot capacitance is isolated: Cdivot = C1 - C2 - C3. This segmentation approach enables reliable divot detection while maintaining measurement precision by eliminating contributions from other capacitance sources.
Solution Approach 2:
Test structures with specifically positioned contacts are introduced as intermediaries to enable indirect measurement of divot characteristics. The first contact is positioned where gate lines cross the STI boundary, while second and third contacts are positioned over the active region and STI region respectively. These intermediary measurement points allow the divot capacitance to be extracted through mathematical subtraction, solving the precision problem of directly measuring divot properties.
2Productivity
If traditional destructive testing methods are used to detect divots, then measurement precision can be achieved, but productivity is reduced due to inability to perform inline monitoring
Solution Approach 1:
The patent replaces destructive mechanical testing methods with a non-destructive electrical capacitive measurement system. Instead of physically sectioning or damaging the device to measure divots, the invention uses electrical contacts to measure capacitance, which can be performed inline during manufacturing. This substitution maintains sufficient measurement precision for process control while enabling continuous productivity.
Solution Approach 2:
The measurement system uses the device's own gate lines and gate dielectric as part of the capacitive sensing structure. The gate lines serve dual purposes: as functional circuit elements and as one plate of the capacitor for measurement. This self-service approach eliminates the need for separate external measurement apparatus, enabling inline monitoring without compromising measurement precision.
3Reliability
If gate material is deposited to fill divots, then device functionality is restored, but device complexity increases due to potential foot shorts and yield loss
Solution Approach 1:
The patent implements a feedback mechanism where capacitive measurements are taken during manufacturing to detect divot formation. The measured divot capacitance is compared against thresholds to determine whether remedial action (such as selective etching or additional deposition) is needed. This feedback loop prevents the need for blanket gate material deposition, reducing the risk of foot shorts and simplifying the overall process while maintaining device functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables non-destructive, early detection of divot depth, preventing yield issues by providing accurate process control feedback and reducing the risk of 'foot shorts' in semiconductor devices.
Implementation Method 1
measuring a first capacitance at a first region where at least one first gate line crosses over a boundary junction between a shallow trench isolation (STI) region and an active region
Data Source
AI summary
Approaches for characterizing a shallow trench isolation (STI) divot depth are provided. The approach includes measuring a first capacitance at a first region of a substrate where at least one first gate line crosses over a boundary junction between a STI region and an active region. The approach also includes measuring a second capacitance at a second region of the substrate where at least one second gate line crosses over the active region. The approach further includes calculating a capacitance associated with a divot at the first region based on a difference between the first capacitance at the first region and the second capacitance at the second region.