Capacitive DRAM Pixel Circuit for High-Resolution LCDs
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Solution Overview
Problem
Liquid crystal display panels face challenges in achieving high resolution and maintaining a high transmissive aperture ratio while supporting both analog and memory display modes, particularly due to the large area required for SRAM and difficulties in integrating SRAM within subpixels for high display resolution.
Innovation Solution
A liquid crystal display panel utilizing a capacitive element as DRAM, with a pixel circuit comprising switch elements that allow for self-refresh and self-inverting functions, enabling the use of DRAM without reducing the transmissive aperture ratio and allowing for high resolution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If SRAM is used for memory within sub pixels to enable memory display mode, then power consumption is reduced, but the area required increases and transmissive aperture ratio decreases
Solution Approach 1:
The patent extracts the memory function from traditional SRAM and implements it using a capacitive element that can operate in both analog and memory display modes. This extraction allows the system to achieve memory display mode power savings without requiring large SRAM areas, as the capacitive element serves dual purposes: analog gray-scale holding and memory-mode binary state storage.
Solution Approach 2:
The capacitive element is designed to perform multiple functions: it serves as a holding capacitance for analog gray-scale potential in analog display mode, and as a memory element for binary information in memory display mode. This multi-functionality eliminates the need for separate SRAM structures, thereby maintaining high transmissive aperture ratio while enabling power-saving memory display mode.
2Manufacturing precision
If SRAM is integrated within sub pixels to achieve high resolution, then display resolution improves, but the transmissive aperture ratio is reduced due to large SRAM area requirements
Solution Approach 1:
The patent extracts the memory function from traditional SRAM and implements it using a capacitive element that can operate in both analog and memory display modes. This extraction allows the system to achieve memory display mode power savings without requiring large SRAM areas, as the capacitive element serves dual purposes: analog gray-scale holding and memory-mode binary state storage.
Solution Approach 2:
The capacitive element is designed to perform multiple functions: it serves as a holding capacitance for analog gray-scale potential in analog display mode, and as a memory element for binary information in memory display mode. This multi-functionality eliminates the need for separate SRAM structures, thereby maintaining high transmissive aperture ratio while enabling power-saving memory display mode.
3Adaptability or versatility
If traditional pixel circuits with separate memory elements are used, then memory display mode is enabled, but device complexity increases
Solution Approach 1:
The capacitive element is designed to perform multiple functions: it serves as a holding capacitance for analog gray-scale potential in analog display mode, and as a memory element for binary information in memory display mode. This multi-functionality eliminates the need for separate SRAM structures, thereby maintaining high transmissive aperture ratio while enabling power-saving memory display mode.
Solution Approach 2:
The patent merges the analog holding capacitance function and the memory storage function into a single capacitive element structure. This consolidation eliminates the need for separate memory circuits and control logic, thereby reducing pixel circuit complexity while maintaining the ability to operate in both analog and memory display modes.
Data Source
AI summary
A LCD panel is proposed, which meets analog display mode and memory display mode. The LCD panel includes a capacitive element, first to third switch elements, and a circuit. The first switch element turns ON during a first operation for writing pixel potential from signal line to the capacitive element, and turns OFF during a second operation. The second and third switch elements turn OFF during the first operation. The second switch element turns ON during a readout period in the second operation, to read out the pixel potential from the capacitive element. The third switch element turns ON during a write period in the second operation, to rewrite the pixel potential into the capacitive element. The circuit restores a logic level of the pixel potential read out from the capacitive element, and rewrites inversion of the restored logic level to the capacitive element.


