Capacitive Digital-to-Time Converter for PVT-Stable Low-Area Timing
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Solution Overview
Problem
Conventional digital-to-time converters (DTCs) are sensitive to process, voltage, and temperature variations, and they consume power and semiconductor die area due to the use of complementary metal-oxide semiconductor (CMOS) delay cells and resistive digital-to-analog converters (DACs).
Innovation Solution
A digital-to-time converter architecture that employs a capacitive digital-to-analog converter (CDAC) as both a digitally-controlled voltage generator and charging capacitor, combined with a switched capacitor voltage-to-current converter and current mirror to generate a charging current, improving power efficiency and robustness to process, voltage, and temperature variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If CMOS delay cells are used to form a DTC, then the DTC can be implemented with standard CMOS technology, but the DTC becomes sensitive to process, voltage, and temperature variations
Solution Approach 1:
The patent replaces the mechanical/electronic delay cell approach with a capacitive charging approach. Instead of using CMOS delay cells that are sensitive to PVT variations, the invention uses a capacitor that is charged by a current mirror circuit, where the time delay is determined by the RC time constant rather than by the delay characteristics of CMOS gates. This substitution eliminates the direct sensitivity to PVT variations that plagues delay-cell-based DTCs.
Solution Approach 2:
The patent changes the fundamental operating parameter from delay time (which is PVT-sensitive) to capacitance charging time. By using a capacitor with a well-defined time constant and a current mirror to charge it, the system achieves PVT insensitivity. The current mirror replicates reference currents accurately, and the capacitor charging follows a predictable exponential curve, making the time delay robust against process, voltage, and temperature variations.
2Measurement precision
If a resistive DAC is used to convert the digital word into an initial voltage, then the DTC can achieve the required resolution, but the DAC consumes power and semiconductor die area
Solution Approach 1:
The patent extracts and removes the resistive DAC from the system entirely. Instead of using a resistive DAC to generate the initial voltage, the invention uses a capacitive DAC that directly charges the capacitor to a voltage proportional to the digital input code. This extraction eliminates the power-consuming resistive network while maintaining the resolution requirement through the capacitive charge redistribution mechanism.
Solution Approach 2:
The patent substitutes the resistive DAC with a capacitive DAC. The capacitive DAC uses an array of capacitors that are switched to charge the main capacitor according to the digital input code, eliminating the need for resistive elements. This substitution dramatically reduces power consumption since capacitive switching consumes negligible power compared to resistive current flow, while maintaining the required resolution through precise capacitor ratio matching.
3Measurement precision
If a resistive DAC is used to convert the digital word into an initial voltage, then the DTC can achieve the required resolution, but the DAC occupies semiconductor die area
Solution Approach 1:
The patent extracts and removes the resistive DAC from the system entirely. Instead of using a resistive DAC to generate the initial voltage, the invention uses a capacitive DAC that directly charges the capacitor to a voltage proportional to the digital input code. This extraction eliminates the power-consuming resistive network while maintaining the resolution requirement through the capacitive charge redistribution mechanism.
Solution Approach 2:
The patent changes the fundamental approach from resistive voltage division to capacitive charge storage. By using a capacitive DAC with binary-weighted capacitors, the system achieves the same resolution function with dramatically reduced area. The capacitive approach allows for higher density integration since capacitors can be implemented with much smaller footprint than precision resistors, especially when using switched-capacitor techniques.
4Ease of operation
If conventional DTC architectures are used, then the basic functionality is achieved, but the DTC suffers from process, voltage, and temperature variations
Solution Approach 1:
The patent employs a current mirror circuit that provides implicit feedback for PVT compensation. The current mirror replicates the reference current with high accuracy by matching transistor geometries and using common-centroid layout techniques. This feedback mechanism ensures that the charging current maintains a stable relationship with the reference voltage and capacitor value across PVT variations, thereby improving robustness while maintaining basic DTC functionality.
Solution Approach 2:
The patent uses a common-centroid layout technique for the current mirror transistors and capacitor array to achieve equipotentiality in terms of PVT conditions. By placing all critical components in a symmetric arrangement that experiences identical process, voltage, and temperature conditions, the system achieves immunity to gradient effects and systematic variations, thereby improving PVT robustness without compromising basic functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution reduces power consumption and semiconductor die area while enhancing stability and density, allowing for more integrated circuits in the same die space and improved robustness to variations, making it suitable for applications like fractional-N phase-locked loops and other electronic systems.
Implementation Method 1
a switched capacitor voltage-to-current converter configured to convert a reference voltage into a first current
Implementation Method 2
a current mirror configured to convert the first current into a second current and to provide the second current to charging capacitor through the common terminal
Implementation Method 3
a charging capacitor including a common terminal
Data Source
AI summary
A digital-to-time converter (DTC) converts a digital code into a time delay using a capacitor digital-to-analog converter (CDAC) that functions as a charging capacitor. The DTC includes a switched capacitor voltage-to-current converter for the formation of a charging current (or a discharging current) for charging (or for discharging) the charging capacitor responsive to a triggering clock edge that begins the time delay. A comparator compares a voltage on the charging capacitor to a threshold voltage to determine an end of the time delay.