Capacitive Filling Structure Layout for Higher CMOS Cell Capacitance
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Solution Overview
Problem
The capacitive value of conventional MOS capacitive structures in integrated circuits is limited by the composition of complementary wells of CMOS type standard cells, which occupy surface area without contributing significantly to the capacitive effect, and require separation distances that further reduce effective surface area.
Innovation Solution
Introduce a discontinuity in the arrangement of complementary wells at capacitive filling structures, allowing standard cells to share a well with adjacent rows, and use conductive structures to ensure electric continuity without well taps, thereby enlarging the capacitive interface and reducing resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional MOS capacitive structures are used with complementary wells, then the capacitive structure can be formed in standard CMOS cells, but the capacitive value per unit area is limited due to well taps and separation distances occupying surface area
Solution Approach 1:
The patent extends the capacitive structure vertically into the substrate by forming a conductive armature that penetrates through the first well to contact the second well. This vertical extension increases the capacitive interface area without occupying additional horizontal surface area, thereby increasing capacitive value per unit area.
Solution Approach 2:
The conductive armature is nested within the well structure, with the first well formed in the second well. The capacitive interface is formed between the conductive armature and the first well, while the first well itself is nested within the second well, creating a multi-layered nested structure that maximizes capacitive area within the available vertical space.
2Reliability
If well taps are provided to operate the well in depletion mode, then the well can be polarized to non-zero voltage, but the well taps occupy surface area that only slightly contributes to the capacitive effect
Solution Approach 1:
Instead of using lateral well taps that occupy surface area, the patent uses a vertical conductive armature that penetrates through the first well to contact the second well. This vertical connection provides the necessary electrical connection without occupying significant horizontal surface area, maintaining depletion mode operation while maximizing capacitive area.
3Reliability
If longitudinal ends of trenches are separated from neighboring wells to avoid current flow, then turned-on-transistor effect is avoided, but the separation distance occupies surface area that does not contribute to capacitive effect
Solution Approach 1:
The patent moves the electrical connection from a lateral arrangement to a vertical arrangement. The conductive armature penetrates vertically through the first well to contact the second well, eliminating the need for lateral separation distances. This vertical connection maintains proper electrical isolation in the horizontal plane while providing the necessary electrical connection vertically, thereby maximizing the capacitive interface area.
4Adaptability or versatility
If standard cells are arranged in rows with fixed width, then standard cell compatibility is maintained, but the capacitive filling structure must fit within the constrained space
Solution Approach 1:
The patent forms the capacitive filling structure by extending vertically into the substrate rather than expanding horizontally. The conductive armature penetrates through the first well to contact the second well, creating a vertical capacitive interface that fits within the fixed width constraints of standard cell rows while maintaining standard cell compatibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly increases the capacitive value per unit area, reduces the need for well taps, and maintains compatibility with standard cell combinations, without additional manufacturing costs.
Implementation Method 1
a capacitive interface between a conductive armature and the first well
Data Source
AI summary
The integrated circuit includes a logic part including standard cells arranged in parallel rows along a first direction and in an alternation of complementary semiconductor wells. Among the standard cells, at least one capacitive filling structure belongs to two adjacent rows and includes a capacitive interface between a conductive armature and the first well, the extent of the second well in the first direction being interrupted over the length of the capacitive filling structure so that the first well occupies in the second direction the width of the two adjacent rows of the capacitive filling structure. A conductive structure electrically connects the second well on either side of the capacitive filling structure.