Capacitive Integrate-and-Fold Charge Converter for Wide Dynamic Range
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional charge-to-digital conversion circuits in X-ray imaging systems face challenges in achieving low-noise, high-dynamic range signals at frequencies from 500 Hz to 100 kHz, requiring large integration capacitors and being sensitive to thermal drift and parasitic capacitance.
Innovation Solution
A capacitance-based 'integrate and fold' method using an operational transconductance amplifier with an integrating capacitor and a fold capacitor, where the fold capacitor is switchably coupled to a fold buffer or the integrating capacitor for charge transfer, enabling faster sampling rates and lower power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a large integration capacitor is used to accommodate large analog input signal range, then the dynamic range is improved, but the physical size and power consumption increase
Solution Approach 1:
The patent divides the integration capacitor into multiple smaller capacitors (first integration capacitor and second integration capacitor) that can be selectively connected. This segmentation allows the system to achieve the functionality of a large capacitor when needed while using smaller capacitors during normal operation, thus maintaining dynamic range without permanently requiring large physical area.
Solution Approach 2:
The patent employs dynamic switching between different capacitor configurations using switches. The integration capacitor can be dynamically reconfigured between a first configuration (with smaller effective capacitance) and a second configuration (with larger effective capacitance), allowing the system to adapt its capacitance value based on signal requirements without permanently occupying the space of the largest possible capacitor.
2Adaptability or versatility
If conventional current-based folding is used to extend dynamic range, then the analog input signal range is improved, but the circuit complexity and sensitivity to parasitic capacitance increase
Solution Approach 1:
The patent replaces conventional current-based folding mechanisms with a capacitance-based folding approach. Instead of using complex current mirrors and current subtraction circuits, the invention uses capacitor charging and discharging operations to achieve the same dynamic range extension, thereby simplifying the circuit architecture and reducing sensitivity to parasitic capacitance effects.
Solution Approach 2:
The patent introduces a fold capacitor as an intermediary element that mediates between the integration capacitors and the rest of the circuit. This fold capacitor enables charge transfer and folding operations without requiring complex current-based circuits, thereby reducing overall circuit complexity while maintaining the ability to handle large analog input signal ranges.
3Productivity
If high sampling rates are achieved in conventional ADC circuits, then the conversion speed is improved, but the power consumption increases
Solution Approach 1:
The patent employs periodic charging and discharging operations of the integration capacitors and fold capacitor to achieve high sampling rates. By using periodic charge transfer operations instead of continuous high-power circuit operation, the system can achieve fast sampling while reducing average power consumption. The switches periodically connect and disconnect capacitors in a controlled sequence to perform conversion operations efficiently.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for smaller physical components, reduced power requirements, and improved thermal stability, enabling broader applications with enhanced dynamic range and reduced thermal drift, while being less sensitive to parasitic capacitance.
Implementation Method 1
an integrating capacitor for storing a charge input selectively provided by a sensor diode
Implementation Method 2
a fold capacitor switchably coupled either to a fold voltage source via a fold buffer for charging the fold capacitor to a predetermined fold charge value, or to the integrating capacitor for selectively removing at least a portion of the stored charge input
Data Source
AI summary
A circuit for converting a charge signal into a binary format of output bits comprises: an integration circuit including an operational transconductance amplifier having an inverting input terminal and an output terminal, an integrating capacitor connected between the inverting input terminal and the output terminal, the integrating capacitor for storing a charge input selectively provided by a sensor diode; and a folding circuit having a fold capacitor, the fold capacitor switchably coupled either to a fold voltage source via a fold buffer for charging the fold capacitor to a predetermined fold charge value, or to the integrating capacitor for selectively removing at least a portion of the stored charge input.