Differential Capacitive Gate Driver for Stable High-Slew Bridge Switching
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Solution Overview
Problem
Existing gate driver circuits for half bridge or full bridge output stages face challenges in achieving high slew rate and low latency while minimizing parasitic inductance effects, which can lead to damage from current spikes and spurious turn-on/off due to supply voltage oscillations, and are often costly and inefficient.
Innovation Solution
A gate driver circuit incorporating a differential capacitive level shifter and set-reset latch with feedback circuits and hysteresis modules to stabilize logic state changes, reducing sensitivity to supply voltage oscillations and improving efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high slew rate signals are used to increase frequency and reduce commutation losses, then efficiency and performance improve, but parasitic inductance causes current spikes and supply voltage oscillations that can damage components
Solution Approach 1:
The circuit applies preliminary anti-action by using the hysteresis module to predict and prevent spurious logic state changes before they occur. The hysteresis threshold creates a preventive barrier against voltage oscillations that could cause incorrect switching, thereby counteracting the harmful effects of parasitic inductance before they manifest as damage or errors.
Solution Approach 2:
The feedback module continuously monitors the logic state of the output transistor and feeds this information back to the level shifter and hysteresis module. This closed-loop feedback mechanism detects and corrects potential errors caused by voltage oscillations, ensuring stable operation even at high slew rates where parasitic effects are significant.
2Device complexity
If conventional level shifters are used without hysteresis, then circuit complexity is reduced, but the circuit becomes sensitive to supply voltage oscillations causing spurious turn-on/off
Solution Approach 1:
The hysteresis module implements partial action by applying hysteresis only to the critical logic state transitions that are susceptible to voltage oscillations. Rather than redesigning the entire level shifter, hysteresis is selectively applied to the threshold detection mechanism, providing sufficient noise immunity with minimal additional complexity.
Solution Approach 2:
The hysteresis module acts as an intermediary between the capacitive level shifter and the logic state determination. It mediates the transition by introducing a threshold band that filters out small voltage oscillations, allowing the circuit to maintain reliability without requiring complete redesign of the level shifting mechanism.
3Loss of time
If fast reaction to output level changes is required, then low latency from digital input to analog output is needed, but high frequency signals increase susceptibility to parasitic effects
Solution Approach 1:
The capacitive level shifter performs preliminary action by rapidly transferring the logic state change from the digital domain to the analog domain before parasitic effects can significantly impact the signal. The direct capacitive coupling enables extremely fast transition without requiring complex intermediate stages, thereby minimizing latency while maintaining immunity to parasitic inductance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables fast and efficient level shifting with low power consumption, preventing spurious logic state changes and maintaining high performance even under high slew rate conditions, while reducing costs and area requirements.
Implementation Method 1
a capacitive level shifter circuit receiving said input signals at a low voltage level and shifting said input signals at a low voltage level to a high voltage level
Implementation Method 2
hysteresis module stabilizing logic state changes
Data Source
AI summary
A gate driver circuit for a half bridge or full bridge output driver stage having a high side branch connected to one or more high side transistors and a low side branch connected to one or more low side transistors. A high side gate driver and a low side gate driver receive input signals at a low voltage level and output signals at a high voltage level as gate driving signals for the high side transistors and low side transistors. Each of the high side and the low side branches of the gate driver includes a set-reset latch having a signal output that is fed as a gate signal to the corresponding transistor of the half bridge or full bridge driver. A differential capacitive level shifter circuit receives the input signals at a low voltage level and outputs high voltage signals to drive the set and reset inputs of the set-reset latch.