Capacitively Coupled Gate Structure for Low-HCI Power Semiconductors
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Solution Overview
Problem
Semiconductor devices, particularly in automotive BCD applications, face challenges with high power densities requiring reduced specific on-resistance (RSP) and increased breakdown voltages, while also needing to mitigate hot carrier injection (HCI) and integration issues with existing isolation techniques like STI and LOCOS.
Innovation Solution
The implementation of laterally and vertically capacitively coupled gate conductor structures over a thin dielectric layer, which reduces hot carrier injection and improves specific on-resistance by controlling electric field build-up without requiring expensive silicon on insulator (SOI), shallow trench isolation (STI), or localized oxidation (LOCOS) type isolations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional isolation techniques (STI, LOCOS) are used in smaller geometry devices, then device isolation is achieved, but integration issues, cost increases, and reliability problems occur
Solution Approach 1:
The patent extracts and eliminates the need for traditional isolation techniques (STI, LOCOS) by using a simplified device structure that achieves isolation through the intrinsic properties of the semiconductor layers and junctions, thereby reducing process complexity and integration issues while maintaining reliability
Solution Approach 2:
The patent replaces expensive and complex isolation processes with simpler, more cost-effective methods that use standard semiconductor processing techniques, reducing manufacturing costs and process steps while achieving the required isolation functionality
2Power
If higher power densities are implemented in BCD applications, then power capability is improved, but specific on-resistance (RSP) increases
Solution Approach 1:
The patent applies local quality by optimizing the doping profiles and layer structures in specific regions of the device to locally reduce on-resistance where needed while maintaining high breakdown voltage in other regions, enabling high power density with low RSP
Solution Approach 2:
The patent changes key device parameters including doping concentrations, layer thicknesses, and junction depths to achieve the optimal balance between power density and specific on-resistance, allowing the device to operate at higher power levels with improved RSP performance
3Reliability
If breakdown voltage is increased to meet higher voltage requirements, then voltage capability is improved, but hot carrier injection (HCI) degradation increases
Solution Approach 1:
The patent converts the potentially harmful high electric fields that cause HCI into a beneficial effect by carefully engineering the field distribution through optimized junction structures and doping profiles, which spread out the electric field to reduce peak fields and minimize HCI while maintaining high breakdown voltage
Solution Approach 2:
The patent introduces intermediary layers and structures that mediate between the high voltage requirements and the HCI problem, using carefully designed intermediate regions to control electric field distribution and protect against hot carrier injection while achieving the required breakdown voltage
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables semiconductor devices with improved breakdown voltage performance, reduced RSP, and enhanced resistance to HCI, while maintaining cost-effectiveness and reliability, particularly suitable for automotive applications with higher reliability requirements.
Implementation Method 1
capacitively coupled gate conductor structures that are configured to control electric field build-up in portions of the semiconductor device
Data Source
AI summary
In an example, a semiconductor device includes a region of semiconductor material, a first dielectric over the region of semiconductor material, a first gate conductor over a first portion of the first dielectric, and a second gate conductor over a second portion of the first dielectric and laterally spaced apart from the first gate conductor. A first conductor is coupled to the first gate conductor and a second conductor coupled to the second gate conductor and laterally separated from the first conductor by a first spacing. A second dielectric is within the first spacing. The first conductor and the second conductor are laterally capacitively coupled, the first gate conductor is vertically capacitively coupled to the region of semiconductor material, and the second gate conductor is vertically capacitively coupled to the region of semiconductor material.