Capacitive Input Choppers for High Common-Mode Voltage Sensing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Instrumentation amplifiers and analog-to-digital converters face challenges in measuring small differential-mode voltages across a current-sense resistor in the presence of large common-mode voltages, as existing solutions like transformers are costly and difficult to integrate, and capacitive-coupled input choppers require peak-to-peak clock voltages exceeding diode and threshold voltages for reliable operation.
Innovation Solution
The use of capacitive-coupled input choppers with latches and floating wells allows for robust switching and protection against high common-mode voltages, enabling larger differential-mode input voltages without drawing common-mode supply current, by replacing diodes with latches and using series capacitors to manage gate voltages and protect against voltage surges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If transformers are used for sensing beyond supply-rail voltage, then measurement capability is improved, but cost and circuit board area increase significantly
Solution Approach 1:
The patent replaces the mechanical/physical transformer component with an electronic capacitive-coupled chopper circuit. This substitution eliminates the need for bulky transformers while achieving the same function of sensing differential-mode voltages beyond the supply rail, thereby reducing circuit board area and enabling full integration.
Solution Approach 2:
The patent extracts the voltage sensing function from the transformer and implements it separately through capacitive coupling and chopping circuits. This allows the sensing function to be achieved without the parasitic effects and physical constraints of transformers, enabling measurement beyond supply-rail voltages.
2Reliability
If diodes are used for gate protection in capacitive-coupled choppers, then protection against voltage surges is provided, but peak-to-peak clock voltages must exceed diode and threshold voltages
Solution Approach 1:
The patent introduces latches as intermediary devices between the clock signal and the chopper transistor gates. These latches act as voltage buffers that provide the necessary protection against voltage surges without requiring the clock voltage to exceed diode forward voltage drops, thereby reducing the peak-to-peak clock voltage requirement.
Solution Approach 2:
The patent uses latches to create a copied or replicated voltage level at the gate that is decoupled from the direct clock signal. This copying mechanism allows the gate to receive protected voltage levels without being directly exposed to the full clock voltage swing, eliminating the need for high peak-to-peak clock voltages.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution allows for accurate measurement beyond the supply rail voltage with low input offset and reduced charge injection, enabling efficient operation in high common-mode voltage environments while minimizing circuit complexity and cost.
Implementation Method 1
Each gate is capacitively coupled to a respective clock signal
Data Source
AI summary
A method of differential signal transfer from a differential input Vinp and Vinn having a common mode input voltage that can be higher than the power supply voltage by providing an input chopper having Vinp and Vinn as a differential input, providing an output chopper, capacitively coupling a differential output Voutp and Voutn of the input chopper to a differential input of the output chopper, capacitively coupling a clock to the input chopper and coupling the clock to the output chopper, the clock having a first phase and a second phase opposite from the first phase, the first phase being coupled to the gates of the first and second transistors and the second phase being coupled to the gates of the third and fourth transistors, and providing protection of the gates of the first through fourth transistors from excessive voltages. Various embodiments are disclosed.