Capacitive Inter-Chip Link for Independent Clock Domains
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Solution Overview
Problem
In 3D stacked chip-to-chip communication systems, the need for a common clock signal or dedicated clock channel limits the use of distinct and non-related clock domains, requiring synchronizers that complicate the design and increase power consumption.
Innovation Solution
A self-synchronized communication system with a capacitive or resistive channel, featuring a receiver with an asynchronous input stage and a synchronous output stage, along with high impedance and feedback stages, allows data transmission without a shared clock signal, enabling synchronization with a clock signal independently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a common clock signal or dedicated clock channel is used for synchronization, then communication reliability is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent extracts the clock synchronization function from the data transmission path by using separate asynchronous input and synchronous output stages. The asynchronous input stage receives data without clock synchronization, while the synchronous output stage generates clock-synchronized output data independently, eliminating the need for shared clock channels.
Solution Approach 2:
The patent introduces an intermediary feedback mechanism where the output of the synchronous output stage is fed back to the asynchronous input stage. This feedback loop enables the system to automatically adjust and synchronize without requiring external clock signals, resolving the contradiction between reliability and complexity.
2Reliability
If a common clock signal is transmitted between chips, then synchronization is improved, but power consumption increases
Solution Approach 1:
The patent separates the data transmission function from the clock synchronization function. The asynchronous input stage handles data reception without consuming power for clock distribution, while the synchronous output stage generates synchronization signals locally without requiring transmitted clock signals, thereby reducing power consumption.
Solution Approach 2:
The system performs self-synchronization using internal feedback mechanisms. The synchronous output stage generates clock-synchronized output data based on feedback from the asynchronous input stage, allowing each chip to synchronize independently without requiring power-intensive external clock distribution.
3Adaptability or versatility
If synchronizers are added to enable distinct clock domains, then adaptability is improved, but device complexity increases
Solution Approach 1:
The patent creates a universal receiver structure that can operate with any clock domain configuration. The asynchronous input stage universally accepts data from different clock domains, while the synchronous output stage universally generates synchronized output, making the system adaptable to various clock domain scenarios without requiring domain-specific synchronizers.
Solution Approach 2:
The system achieves self-synchronization through internal feedback, eliminating the need for external synchronizers. The feedback loop automatically adjusts timing relationships, enabling the system to adapt to different clock domains while maintaining simplicity, as each chip synchronizes independently without requiring complex synchronizer circuits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution eliminates the need for clock signal transmission and synchronizers, allowing for reliable and efficient data exchange between chips with non-correlated clock domains, reducing power consumption and design complexity.
Implementation Method 1
a chip-to-chip vertical communication system, based on contactless IO schemes exploiting capacitive coupling as an inter-chip channel
Data Source
Figure 1
Figure 2A~2B
Figure 3~6
AI summary
The invention relates to a communication system for the connection between timing non correlated synchronous devices of the type comprising at least one transmitter (30) and one receiver (40) inserted between a first and a second voltage reference (Vcc, GND) and connected to each other by means of a transmitting channel (25) in correspondence with respective transmitting (TX) and receiving (RX) terminals. Advantageously according to the invention, the receiver (40) comprises at least one synchronous input stage (41) suitable for receiving on said receiving terminal (RX) a datum (D) and associated with a synchronous output stage (42) suitable for transmitting said datum (D) in a synchronised way with a clock signal (CP) on a synchronised receiving terminal (RXs). The invention also relates to a method for transmitting a datum (D) from a transmitter (30) to a receiver (40) interconnected by means of a capacitive channel (25) in a communication system for the connection between independently clocked devices.