Capacitive Interposer Reducing Parasitic Inductance
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Solution Overview
Problem
As clock speeds in integrated circuits increase, existing decoupling solutions become inadequate in minimizing parasitic inductance and reducing the size of electronic devices while maintaining functionality, as capacitive interposers face limitations in reducing inductance and increasing functionality without increasing spatial footprint.
Innovation Solution
A monolithic interposer with a ceramic structure that directly connects an integrated circuit to a printed circuit board, incorporating capacitors with parallel plates and dielectric layers, and featuring conduction paths that allow for direct power and signal feed-through, reducing parasitic inductance and noise while maintaining a minimized footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If decoupling capacitors are positioned nearer to the IC and smaller capacitors with lower inductance values are used, then parasitic inductance is reduced, but device footprint increases and functionality is limited
Solution Approach 1:
The patent combines multiple functions into a single integrated structure: the interposer integrates decoupling capacitors, power feed-through, and signal transmission pathways into one compact component that sits between the IC and PCB, eliminating the need for separate capacitor placements and reducing overall footprint while maintaining low inductance
Solution Approach 2:
The interposer utilizes vertical stacking and three-dimensional integration to achieve multiple functions within a minimized planar footprint, allowing capacitors and conduction paths to be arranged in multiple layers and dimensions rather than spreading out on a single plane
2Object-affected harmful factors
If capacitive interposers are used to reduce parasitic inductance, then inductance is minimized, but functionality is limited to capacitance and decoupling only
Solution Approach 1:
The interposer is designed as a multi-functional component that simultaneously provides decoupling capacitance, power feed-through, signal transmission, and noise filtering capabilities within a single device, making it adaptable to various high-speed electronic applications beyond just capacitance functions
Solution Approach 2:
Multiple electrical functions are merged into the interposer structure, including power delivery, signal routing, and decoupling, allowing a single component to replace what would traditionally require multiple separate components and traces
3Adaptability or versatility
If additional circuit traces are added for power and signal feed-through, then functionality is enhanced, but parasitic inductance and device complexity increase
Solution Approach 1:
The interposer extracts and consolidates the feed-through functionality into its own dedicated structure with optimized low-inductance pathways, separating the power and signal transmission functions from the IC and PCB traces to minimize parasitic effects while maintaining enhanced functionality
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces parasitic inductance and noise in high-speed integrated circuits by providing direct decoupling and filtering capabilities without the need for additional circuit traces, thereby enhancing functionality without increasing the device's spatial requirements.
Implementation Method 1
At least one capacitor is provided. Each capacitor has a plurality of parallel plates with a dielectric there between.
Implementation Method 2
Each capacitor has a plurality of parallel plates with a dielectric there between.
Implementation Method 3
conduction paths between each upper connection of the upper connections and a lower connection of the lower connections
Data Source
AI summary
A capacitive interposer, electronic package having the capacitive interposer and electronic device with the electronic package is described. The interposer has a first planar face and a second planar face. An array of upper connections is on the first planar face and opposing lower connections are on the second planar face with conduction paths between each upper connection of the upper connections and a lower connection of the lower connections. At least one power feed-through capacitor is provided. The capacitor is mounted on the first planar face with the first external termination in direct electrical contact with a first upper connection and the second external termination is in direct electrical contact with a second upper connection. At least one upper connection, first external termination and second external termination are arranged for direct electrical contact with element contact pads of a common element.