Capacitive Isolation Device With Enhanced Dielectric Layer
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current capacitive isolators face challenges in achieving high voltage tolerance and reliability due to limitations in breakdown voltage and susceptibility to noise, particularly when incorporating high voltage capacitors in semiconductor dies, which often require off-chip capacitors and result in floating electrical nodes and noise susceptibility.
Innovation Solution
The development of an isolation device with an enhanced isolation layer and trench structures that intercept residue materials to prevent unwanted electrical paths, allowing for capacitive coupling between isolated circuits while maintaining high voltage tolerance, using a substrate with metal layers and passivation layers to create a robust isolation mechanism.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If high voltage capacitors are incorporated into semiconductor dies, then breakdown voltage is improved, but manufacturing complexity and noise susceptibility worsen
Solution Approach 1:
The patent introduces an off-chip capacitor as an intermediary element that bridges the high voltage circuit and low voltage control circuit. This external capacitor serves as the isolation medium, allowing the semiconductor die itself to remain simpler while still achieving high breakdown voltage through the external capacitive isolation structure.
Solution Approach 2:
The patent moves the capacitor from the two-dimensional chip plane to the three-dimensional space outside the chip. By placing the capacitor off-chip, the design achieves high voltage tolerance without constraining the semiconductor manufacturing process, effectively using spatial dimensionality to resolve the contradiction.
2Strength
If capacitors are arranged in series to meet breakdown voltage specification, then breakdown voltage is improved, but reliability worsens due to floating electrical nodes
Solution Approach 1:
The patent extracts the capacitor element from the integrated circuit structure and places it externally. This removal eliminates the floating node problem inherent in on-chip series capacitor configurations, as the external capacitor can be properly grounded and shielded, thereby maintaining high breakdown voltage while improving reliability.
Solution Approach 2:
The off-chip capacitor acts as an intermediary that provides capacitive coupling between isolated circuits while allowing proper grounding and shielding. This external positioning enables the capacitor to serve its isolation function without creating unreliable floating nodes within the semiconductor package.
3Strength
If opto-isolators are used for electrical isolation, then breakdown voltage is improved, but transmission speed worsens due to built-in capacitance
Solution Approach 1:
The patent replaces the optical mechanism of opto-isolators with an electrical capacitive coupling mechanism. By using capacitive isolation instead of optical isolation, the system achieves comparable or superior breakdown voltage while eliminating the speed limitations imposed by light emission and detection processes and built-in capacitance.
Solution Approach 2:
The patent changes the isolation mechanism from optical to electrical capacitive coupling. This parameter change allows the system to achieve high breakdown voltage through the capacitive structure while maintaining fast transmission speeds by using direct electrical coupling rather than optical conversion processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively increases the breakdown voltage and reliability of capacitive isolators, enabling safe operation in high-voltage systems while allowing signal transmission between isolated circuits without direct electrical current flow, thus addressing the limitations of existing technologies.
Implementation Method 1
an isolation layer positioned between the first capacitive element and the second capacitive element
Implementation Method 2
capacitive isolators may not have the optical degradation issue of the opto-isolators
Data Source
AI summary
An isolation system, isolation device, and Integrated Circuit are disclosed. The isolation system is described to include an integrated circuit chip having a first capacitive plate, a second capacitive plate positioned with respect to the first capacitive plate to enable a capacitive coupling therebetween, an enhanced isolation layer positioned between the first capacitive the second capacitive plate that facilitates an electrical isolation between the first capacitive plate and the second capacitive plate, a first bonding wire that is in electrical communication with the second capacitive plate, and an isolation trench that at least partially circumscribes the first capacitive plate and is positioned between the first capacitive plate and the first bonding wire.