Capacitive Isolation Circuit for Semiconductor Package
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Solution Overview
Problem
Conventional semiconductor isolation methods are limited by the thickness of dielectric stacks, which restricts maximum isolation voltage and increases the risk of electrostatic discharge (ESD), degrading insulating properties and limiting the distance through insulation.
Innovation Solution
A capacitive isolation circuit is implemented outside the semiconductor die within a semiconductor package, using a dielectric material with conductive layers to provide a distance through insulation greater than 0.1 mm, enabling galvanic isolation and high-voltage communication while reducing ESD risks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional capacitive isolators integrate the isolator within the semiconductor component using metal capacitance between top metal layer and bottom metal layers, then the isolation structure is compact, but the distance through insulation is limited and maximum isolation voltage is reduced
Solution Approach 1:
The isolator is extracted from the semiconductor component and placed outside it. The patent describes that the isolator may be disposed outside the first semiconductor die and the second semiconductor die, allowing the distance through insulation to be increased without being constrained by the internal metal layer structure of the semiconductor component.
Solution Approach 2:
The isolation structure transitions from a planar integration within the semiconductor component to a three-dimensional arrangement where the isolator is positioned externally. This allows the distance through insulation to extend beyond the thickness of the semiconductor component's dielectric stacks.
2Reliability
If the dielectric stack thickness is increased to improve isolation voltage, then maximum isolation voltage is improved, but the risk of electrostatic discharge (ESD) degrading insulating properties increases
Solution Approach 1:
The isolator acts as an intermediary element between the semiconductor components, providing a dedicated capacitive coupling structure with optimized dielectric materials and thickness. This intermediary structure allows for controlled insulation distance that achieves high isolation voltage while managing ESD risks through proper dielectric selection and configuration.
3Volume of moving object
If conventional isolators use thin polyimide tape or oxide layers between metal layers, then the isolation structure is compact, but insulation performance decreases and ESD risk increases
Solution Approach 1:
The isolator is extracted from the semiconductor component and placed outside it. The patent describes that the isolator may be disposed outside the first semiconductor die and the second semiconductor die, allowing the distance through insulation to be increased without being constrained by the internal metal layer structure of the semiconductor component.
Solution Approach 2:
The isolator employs composite structures with multiple dielectric layers and materials, including the dielectric member with first and second major surfaces, and conductive members positioned on opposite sides. This composite approach allows optimization of both insulation performance and ESD protection while maintaining a compact overall structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances insulation performance, supports high voltage levels, and reduces the risk of electrostatic discharge, allowing for safe and efficient data transmission across insulation barriers in compact semiconductor packages.
Implementation Method 1
The capacitive isolation circuit may include a first capacitor network having first and second conductive layers with a dielectric material disposed between the first and second conductive layers
Implementation Method 2
The dielectric material may include one of a glass material and a ceramic material. The capacitive isolation circuit may include a dielectric thickness that provides a distance through insulation equal to or greater than 0.1 mm
Data Source
AI summary
In some general aspects, an apparatus may include a first semiconductor die, a second semiconductor die, and a capacitive isolation circuit being coupled to the first semiconductor die and the second semiconductor die. The capacitive isolation circuit may be disposed outside of the first semiconductor die and the second semiconductor die. The first semiconductor die, the second semiconductor die, and the capacitive circuit may be included in a molding of a semiconductor package.