Capacitive Isolation Device With Stacked Metal Layers
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Solution Overview
Problem
Conventional galvanic isolators, such as opto-isolators, face degradation issues due to optical signal degradation, while capacitive isolators struggle with high voltage tolerance due to limitations in semiconductor die fabrication, leading to additional costly post-processing steps and potential breakdowns.
Innovation Solution
The isolation device employs a configuration with multiple metal layers and isolation layers, including trench isolation layers, to create a capacitively coupled signal across a substrate, enhancing high voltage tolerance and preventing breakdowns by increasing the distance between metal plates and using materials like silicon dioxide and polyimide for isolation layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional opto-isolators are used for galvanic isolation, then signal transmission between isolated circuits is enabled, but optical degradation occurs over time reducing reliability
Solution Approach 1:
The patent replaces the optical system (emitter and receiver) with an electrical capacitive coupling system. The isolation capacitor directly couples the input and output circuits through electrical fields, eliminating optical components that degrade over time. This substitution of optical mechanism with electrical mechanism resolves the reliability issue while maintaining galvanic isolation.
Solution Approach 2:
The patent creates an electrical field copy of the input signal through the isolation capacitor to transfer signals between isolated circuits. Instead of using optical copies that degrade, the capacitive coupling preserves signal integrity by maintaining electrical field relationships without physical degradation of transmission medium.
2Reliability
If high voltage capacitors are incorporated into semiconductor die for capacitive isolation, then galvanic isolation with signal transmission is achieved, but manufacturing complexity and cost increase due to post-processing steps
Solution Approach 1:
The patent merges the isolation capacitor fabrication with the standard semiconductor manufacturing process. The capacitor structures are formed using the same deposition, etching, and doping steps already required for the logic circuits, eliminating separate post-processing steps. This integration reduces manufacturing complexity while achieving high voltage tolerance.
Solution Approach 2:
The patent designs capacitor structures that serve dual purposes: they provide galvanic isolation functionality while also being formed using universal semiconductor process steps. The same process equipment and materials used for logic device fabrication are utilized for capacitor creation, making the high voltage isolation capability universal across different circuit designs without adding process complexity.
3Ease of manufacture
If MOS capacitors or double layer poly-silicon capacitors are used in semiconductor dies, then standard fabrication processes are utilized, but high voltage breakdown occurs due to insufficient distance between gate and substrate
Solution Approach 1:
The patent transitions from planar capacitor structures to three-dimensional stacked capacitor architectures. By stacking capacitor plates vertically in multiple layers with insulating materials between them, the effective distance between conductive elements is increased in the vertical dimension while maintaining a compact footprint. This dimensional change enables high voltage tolerance without requiring larger lateral dimensions or additional process steps.
Solution Approach 2:
The patent employs composite dielectric structures combining multiple insulating materials with different properties. High-k dielectric layers are stacked with low-k spacer layers to achieve both high capacitance and high breakdown voltage. The composite structure leverages the strengths of different materials: high-k materials provide capacitance while thin low-k layers provide voltage isolation, enabling standard processes to achieve high voltage tolerance.
4Ease of manufacture
If overlapping metal layers in semiconductor dies are used for isolation, then standard fabrication processes are utilized, but capacitance value is too low for effective isolation
Solution Approach 1:
The patent stacks capacitor plates in multiple vertical layers rather than relying on lateral overlapping. This vertical stacking in the third dimension dramatically increases the effective capacitance area without requiring additional lateral space or process complexity. The stacked architecture provides sufficient isolation capacitance while maintaining compatibility with standard semiconductor fabrication processes.
Solution Approach 2:
The patent uses composite dielectric structures with high-k materials to achieve high capacitance values in a compact form factor. The high-k dielectric layers provide increased capacitance per unit area, allowing effective isolation capacitance to be achieved within the constraints of standard fabrication processes and device footprint.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively isolates high voltage circuits while maintaining high capacitance, preventing breakdowns and reducing the need for costly post-processing steps, thus improving the reliability and efficiency of signal transmission across voltage-isolated circuits.
Implementation Method 1
an isolation capacitor configured to electrically isolate the first circuit from the second circuit, the capacitively coupled signal being transmitted from the first circuit to the second circuit through the isolation capacitor
Implementation Method 2
using materials like silicon dioxide and polyimide for isolation layers
Data Source
AI summary
In one embodiment, an isolation device has a substrate, a metal plate, a conductive layer, first and second isolation layers are disclosed. The conductive layer may be formed within the substrate. The conductive layer may be arranged coupled to the metal plate, so as to receive a capacitively coupled signal from the metal plate. The first and second isolation layers may be sandwiched between the metal plate and the conductive layer. In another embodiment, an isolation device comprising a semiconductor substrate, a topmost metal layer and a plurality of additional metal layers is disclosed. The isolation device further comprises an isolation capacitor formed using the topmost metal layer and a conductive layer coupled to at least one of the plurality of additional metal layers.