Capacitive Isolator Structure for Higher Breakdown and Lower Interference
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Solution Overview
Problem
Conventional capacitive isolators face challenges with reduced signal transmission capacity due to parasite resistance-capacitor networks, leading to increased interference between signals, and increasing the distance between electrode plates to mitigate this issue results in a larger semiconductor die footprint and higher costs.
Innovation Solution
The capacitive isolator design includes a substrate with shallow trench isolation regions, polysilicon layers, and multiple metal plates with specific dielectric layers, incorporating an intermediate metal plate to enhance breakdown voltage while maintaining a low profile, and an isolation structure with n-type and p-type pickups to reduce signal interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the distance between electrode plates is increased to reduce signal interference, then signal transmission quality is improved, but the semiconductor die footprint increases and manufacturing cost increases
Solution Approach 1:
The patent introduces an intermediate metal plate positioned vertically between the bottom and top metal plates, utilizing the vertical dimension to reduce parasitic coupling. This intermediate plate is positioned at a specific height and has a width less than the bottom metal plate, creating a three-dimensional structure that reduces signal interference without increasing the horizontal footprint of the device.
Solution Approach 2:
The intermediate metal plate acts as a mediator structure between the bottom and top metal plates. It is positioned at a specific vertical distance from the bottom metal plate and has controlled dimensions (width less than bottom metal plate) to reduce parasitic capacitance and coupling effects while maintaining compact horizontal dimensions.
2Reliability
If the breakdown voltage of capacitive isolator is increased to improve isolation performance, then isolation capability is improved, but device complexity increases
Solution Approach 1:
The capacitive isolator is segmented into three metal plates (bottom, intermediate, and top) separated by dielectric layers. The intermediate metal plate is positioned between the bottom and top plates at a specific vertical distance, creating multiple smaller dielectric gaps that collectively provide higher breakdown voltage while maintaining a compact structure.
Solution Approach 2:
The patent utilizes the vertical dimension by positioning the intermediate metal plate at a specific height between the bottom and top metal plates. This vertical segmentation creates multiple dielectric layers in series, increasing the overall breakdown voltage without significantly increasing the horizontal footprint or overall device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design improves breakdown voltage by 10-20% and reduces signal interference between capacitive isolators, maintaining a compact form factor and enhancing overall performance.
Implementation Method 1
the intermediate metal plate has a width less than that of the bottom metal plate and greater than that of the top metal plate... the design improves breakdown voltage by 10-20%
Implementation Method 2
Displacement current could flow between the two circuits through the capacitive isolator to implement transmission of signals, while the insulating materials between the electrode plates provide isolation for low frequency voltage signals
Implementation Method 3
a shallow trench isolation region coupled to the substrate; a polysilicon layer disposed above the shallow trench isolation region
Data Source
AI summary
A capacitive isolator is developed. Embodiments of the capacitive isolator include a substrate; a shallow trench isolation region coupled to the substrate; a polysilicon layer disposed above the shallow trench isolation region; a bottom metal plate disposed above the polysilicon layer; one or more lower dielectric layers above the bottom metal plate; an intermediate metal plate disposed above the one or more lower dielectric layers; and a top metal plate disposed above the intermediate metal plate. A semiconductor device including two capacitive isolators and an isolation structure disposed between the two capacitive isolators is also developed.